Date: Tue, 5 Jul 2011 23:41:36 GMT From: Jakub Wojciech Klama <jceel@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 195784 for review Message-ID: <201107052341.p65NfaZN025286@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@195784?ac=10 Change 195784 by jceel@jceel_cyclone on 2011/07/05 23:41:35 * Added working USB OHCI controller driver with ISP3101 transceiver initialization * Refactored peripheral power control, moved peripheral clocks setup from lpc_pwr to each driver attach() method. Affected files ... .. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/if_lpe.c#4 edit .. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_mmc.c#1 add .. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_ohci.c#3 edit .. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_pwr.c#2 edit .. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_timer.c#2 edit .. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpcreg.h#2 edit .. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpcvar.h#2 edit .. //depot/projects/soc2011/jceel_lpc/sys/boot/fdt/dts/ea3250.dts#4 edit Differences ... ==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/if_lpe.c#4 (text+ko) ==== @@ -60,6 +60,8 @@ #include <dev/mii/mii.h> #include <dev/mii/miivar.h> +#include <arm/lpc/lpcreg.h> +#include <arm/lpc/lpcvar.h> #include <arm/lpc/if_lpereg.h> #include "miibus_if.h" @@ -247,6 +249,9 @@ goto fail; } + /* Enable Ethernet clock */ + lpc_pwr_write(dev, LPC_CLKPWR_MACCLK_CTRL, 0x1f); /* XXX */ + /* Reset chip */ lpe_reset(sc); ==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_ohci.c#3 (text+ko) ==== @@ -47,6 +47,8 @@ #include <sys/malloc.h> #include <sys/priv.h> +#include <sys/kdb.h> + #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -63,12 +65,36 @@ #include <dev/usb/controller/ohci.h> #include <dev/usb/controller/ohcireg.h> +#include <arm/lpc/lpcreg.h> +#include <arm/lpc/lpcvar.h> +#define I2C_START_BIT (1 << 8) +#define I2C_STOP_BIT (1 << 9) +#define I2C_READ 0x01 +#define I2C_WRITE 0x00 +#define DUMMY_BYTE 0x55 +#define lpc_otg_read_4(_sc, _reg) \ + bus_space_read_4(_sc->sc_io_tag, _sc->sc_io_hdl, _reg) +#define lpc_otg_write_4(_sc, _reg, _value) \ + bus_space_write_4(_sc->sc_io_tag, _sc->sc_io_hdl, _reg, _value) +#define lpc_otg_wait_write_4(_sc, _wreg, _sreg, _value) \ + do { \ + lpc_otg_write_4(_sc, _wreg, _value); \ + while ((lpc_otg_read_4(_sc, _sreg) & _value) != _value); \ + } while (0); + static int lpc_ohci_probe(device_t dev); static int lpc_ohci_attach(device_t dev); static int lpc_ohci_detach(device_t dev); +static void lpc_otg_i2c_reset(struct ohci_softc *); + +static int lpc_isp3101_read(struct ohci_softc *, int); +static void lpc_isp3101_write(struct ohci_softc *, int, int); +static void lpc_isp3101_clear(struct ohci_softc *, int, int); +static void lpc_isp3101_configure(device_t dev, struct ohci_softc *); + static int lpc_ohci_probe(device_t dev) { @@ -85,6 +111,9 @@ struct ohci_softc *sc = device_get_softc(dev); int err; int rid; + int i = 0; + uint32_t usbctrl; + uint32_t otgstatus; sc->sc_bus.parent = dev; sc->sc_bus.devices = sc->sc_devices; @@ -97,7 +126,7 @@ rid = 0; sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_io_res) { - device_printf(dev, "cannot map register space\n"); + device_printf(dev, "cannot map OHCI register space\n"); goto fail; } @@ -105,6 +134,8 @@ sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); + device_printf(dev, "virtual register space: 0x%08lx\n", sc->sc_io_hdl); + rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->sc_irq_res == NULL) { @@ -126,8 +157,52 @@ goto fail; } - bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, - OHCI_CONTROL, 0); + usbctrl = lpc_pwr_read(dev, LPC_CLKPWR_USB_CTRL); + usbctrl |= LPC_CLKPWR_USB_CTRL_SLAVE_HCLK | LPC_CLKPWR_USB_CTRL_BUSKEEPER; + lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); + + /* Enable OTG I2C clock */ + lpc_otg_wait_write_4(sc, LPC_OTG_CLOCK_CTRL, + LPC_OTG_CLOCK_STATUS, LPC_OTG_CLOCK_CTRL_I2C_EN); + + /* Reset OTG I2C bus */ + lpc_otg_i2c_reset(sc); + + lpc_isp3101_configure(dev, sc); + + /* Configure PLL */ + usbctrl &= ~(LPC_CLKPWR_USB_CTRL_CLK_EN1 | LPC_CLKPWR_USB_CTRL_CLK_EN2); + lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); + + usbctrl |= LPC_CLKPWR_USB_CTRL_CLK_EN1; + lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); + + usbctrl |= LPC_CLKPWR_USB_CTRL_FDBKDIV(192-1); + usbctrl |= LPC_CLKPWR_USB_CTRL_POSTDIV(1); + usbctrl |= LPC_CLKPWR_USB_CTRL_PLL_PDOWN; + + lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); + do { + usbctrl = lpc_pwr_read(dev, LPC_CLKPWR_USB_CTRL); + if (i++ > 100000) { + device_printf(dev, "USB OTG PLL doesn't lock!\n"); + goto fail; + } + } while ((usbctrl & LPC_CLKPWR_USB_CTRL_PLL_LOCK) == 0); + + usbctrl |= LPC_CLKPWR_USB_CTRL_CLK_EN2; + usbctrl |= LPC_CLKPWR_USB_CTRL_HOST_NEED_CLK_EN; + lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); + lpc_otg_wait_write_4(sc, LPC_OTG_CLOCK_CTRL, LPC_OTG_CLOCK_STATUS, + (LPC_OTG_CLOCK_CTRL_AHB_EN | LPC_OTG_CLOCK_CTRL_OTG_EN | + LPC_OTG_CLOCK_CTRL_I2C_EN | LPC_OTG_CLOCK_CTRL_HOST_EN)); + + otgstatus = lpc_otg_read_4(sc, LPC_OTG_STATUS); + lpc_otg_write_4(sc, LPC_OTG_STATUS, otgstatus | + LPC_OTG_STATUS_HOST_EN); + + lpc_isp3101_write(sc, LPC_ISP3101_OTG_CONTROL_1, + LPC_ISP3101_OTG1_VBUS_DRV); err = ohci_init(sc); if (err) @@ -145,6 +220,106 @@ } static int +lpc_isp3101_read(struct ohci_softc *sc, int reg) +{ + int status; + int i = 0; + + lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, + (LPC_ISP3101_I2C_ADDR << 1) | I2C_START_BIT); + lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, reg); + lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, (LPC_ISP3101_I2C_ADDR << 1) | + I2C_START_BIT | I2C_READ); + lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, I2C_STOP_BIT | DUMMY_BYTE); + + do { + status = lpc_otg_read_4(sc, LPC_OTG_I2C_STATUS); + i++; + } while ((status & LPC_OTG_I2C_STATUS_TDI) == 0 || i < 100000); + + lpc_otg_write_4(sc, LPC_OTG_I2C_STATUS, LPC_OTG_I2C_STATUS_TDI); + + return (lpc_otg_read_4(sc, LPC_OTG_I2C_TXRX) & 0xff); +} + +static void +lpc_otg_i2c_reset(struct ohci_softc *sc) +{ + int ctrl; + int i = 0; + + lpc_otg_write_4(sc, LPC_OTG_I2C_CLKHI, 0x3f); + lpc_otg_write_4(sc, LPC_OTG_I2C_CLKLO, 0x3f); + + ctrl = lpc_otg_read_4(sc, LPC_OTG_I2C_CTRL); + lpc_otg_write_4(sc, LPC_OTG_I2C_CTRL, ctrl | LPC_OTG_I2C_CTRL_SRST); + + do { + ctrl = lpc_otg_read_4(sc, LPC_OTG_I2C_CTRL); + i++; + } while (ctrl & LPC_OTG_I2C_CTRL_SRST); +} + +static void +lpc_isp3101_write(struct ohci_softc *sc, int reg, int value) +{ + int status; + int i = 0; + + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX, + (LPC_ISP3101_I2C_ADDR << 1) | I2C_START_BIT); + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX, + (reg | I2C_WRITE)); + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX, + (value | I2C_STOP_BIT)); + + do { + status = bus_space_read_4(sc->sc_io_tag, sc->sc_io_hdl, + LPC_OTG_I2C_STATUS); + i++; + } while ((status & LPC_OTG_I2C_STATUS_TDI) == 0 || i < 100000); + + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_STATUS, + LPC_OTG_I2C_STATUS_TDI); +} + +static __inline void +lpc_isp3101_clear(struct ohci_softc *sc, int reg, int value) +{ + lpc_isp3101_write(sc, (reg | LPC_ISP3101_REG_CLEAR_ADDR), value); +} + +static void +lpc_isp3101_configure(device_t dev, struct ohci_softc *sc) +{ + lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_UART_EN); + lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_1, ~LPC_ISP3101_MC1_SPEED_REG); + lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_SPEED_REG); + lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_2, ~0); + lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_2, + (LPC_ISP3101_MC2_BI_DI | LPC_ISP3101_MC2_PSW_EN + | LPC_ISP3101_MC2_SPD_SUSP_CTRL)); + + lpc_isp3101_clear(sc, LPC_ISP3101_OTG_CONTROL_1, ~0); + lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_DAT_SE0); + lpc_isp3101_write(sc, LPC_ISP3101_OTG_CONTROL_1, + (LPC_ISP3101_OTG1_DM_PULLDOWN | LPC_ISP3101_OTG1_DP_PULLDOWN)); + + lpc_isp3101_clear(sc, LPC_ISP3101_OTG_CONTROL_1, + (LPC_ISP3101_OTG1_DM_PULLUP | LPC_ISP3101_OTG1_DP_PULLUP)); + + lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_LATCH, ~0); + lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_FALLING, ~0); + lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_RISING, ~0); + + device_printf(dev, + "ISP3101 PHY <vendor:0x%04x, product:0x%04x, version:0x%04x>\n", + (lpc_isp3101_read(sc, 0x00) | (lpc_isp3101_read(sc, 0x01) << 8)), + (lpc_isp3101_read(sc, 0x03) | (lpc_isp3101_read(sc, 0x04) << 8)), + (lpc_isp3101_read(sc, 0x14) | (lpc_isp3101_read(sc, 0x15) << 8))); +} + +static int lpc_ohci_detach(device_t dev) { return (0); ==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_pwr.c#2 (text+ko) ==== @@ -42,6 +42,7 @@ #include <dev/ofw/ofw_bus_subr.h> #include <arm/lpc/lpcreg.h> +#include <arm/lpc/lpcvar.h> struct lpc_pwr_softc { device_t dp_dev; @@ -50,6 +51,8 @@ bus_space_handle_t dp_bsh; }; +static struct lpc_pwr_softc *lpc_pwr_sc = NULL; + static int lpc_pwr_probe(device_t); static int lpc_pwr_attach(device_t); @@ -88,17 +91,21 @@ sc->dp_bst = rman_get_bustag(sc->dp_mem_res); sc->dp_bsh = rman_get_bushandle(sc->dp_mem_res); - /* Enable Timer0 and Timer1 */ - lpc_pwr_write_4(sc, LPC_CLKPWR_TIMCLK_CTRL1, - LPC_CLKPWR_TIMCLK_CTRL1_TIMER0 | - LPC_CLKPWR_TIMCLK_CTRL1_TIMER1); + lpc_pwr_sc = sc; + + return (0); +} - /* Enable Ethernet controller */ - lpc_pwr_write_4(sc, LPC_CLKPWR_MACCLK_CTRL, - 0x1f); - /* XXX */ +uint32_t +lpc_pwr_read(device_t dev, int reg) +{ + return (lpc_pwr_read_4(lpc_pwr_sc, reg)); +} - return (0); +void +lpc_pwr_write(device_t dev, int reg, uint32_t value) +{ + lpc_pwr_write_4(lpc_pwr_sc, reg, value); } static device_method_t lpc_pwr_methods[] = { ==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_timer.c#2 (text+ko) ==== @@ -41,13 +41,12 @@ #include <machine/frame.h> #include <machine/intr.h> -#include <sys/kdb.h> - #include <dev/fdt/fdt_common.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> #include <arm/lpc/lpcreg.h> +#include <arm/lpc/lpcvar.h> struct lpc_timer_softc { device_t lt_dev; @@ -150,6 +149,11 @@ return (ENXIO); } + /* Enable timer clock */ + lpc_pwr_write(dev, LPC_CLKPWR_TIMCLK_CTRL1, + LPC_CLKPWR_TIMCLK_CTRL1_TIMER0 | + LPC_CLKPWR_TIMCLK_CTRL1_TIMER1); + /* Get PERIPH_CLK encoded in parent bus 'bus-frequency' property */ node = ofw_bus_get_node(dev); if (OF_getprop(OF_parent(node), "bus-frequency", &freq, ==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpcreg.h#2 (text+ko) ==== @@ -116,6 +116,21 @@ #define LPC_CLKPWR_START_APR_PIN 0x3c #define LPC_CLKPWR_START_APR_INT 0x2c #define LPC_CLKPWR_USB_CTRL 0x64 +#define LPC_CLKPWR_USB_CTRL_SLAVE_HCLK (1 << 24) +#define LPC_CLKPWR_USB_CTRL_I2C_EN (1 << 23) +#define LPC_CLKPWR_USB_CTRL_DEV_NEED_CLK_EN (1 << 22) +#define LPC_CLKPWR_USB_CTRL_HOST_NEED_CLK_EN (1 << 21) +#define LPC_CLKPWR_USB_CTRL_BUSKEEPER (1 << 19) +#define LPC_CLKPWR_USB_CTRL_CLK_EN2 (1 << 18) +#define LPC_CLKPWR_USB_CTRL_CLK_EN1 (1 << 17) +#define LPC_CLKPWR_USB_CTRL_PLL_PDOWN (1 << 16) +#define LPC_CLKPWR_USB_CTRL_BYPASS (1 << 15) +#define LPC_CLKPWR_USB_CTRL_DIRECT_OUT (1 << 14) +#define LPC_CLKPWR_USB_CTRL_FEEDBACK (1 << 13) +#define LPC_CLKPWR_USB_CTRL_POSTDIV(_x) ((_x & 0x3) << 11) +#define LPC_CLKPWR_USB_CTRL_PREDIV(_x) ((_x & 0x3) << 9) +#define LPC_CLKPWR_USB_CTRL_FDBKDIV(_x) (((_x-1) & 0xff) << 1) +#define LPC_CLKPWR_USB_CTRL_PLL_LOCK (1 << 0) #define LPC_CLKPWR_USBDIV_CTRL 0x1c #define LPC_CLKPWR_MS_CTRL 0x80 #define LPC_CLKPWR_DMACLK_CTRL 0xe8 @@ -145,5 +160,157 @@ #define LPC_CLKPWR_POS0_IRAM_CTRL 0x110 #define LPC_CLKPWR_POS1_IRAM_CTRL 0x114 +/* + * Real time clock. (from UM10326: LPC32x0 User manual, page 566) + */ +#define LPC_RTC_UCOUNT 0x00 +#define LPC_RTC_DCOUNT 0x04 +#define LPC_RTC_MATCH0 0x08 +#define LPC_RTC_MATCH1 0x0c +#define LPC_RTC_CTRL 0x10 +#define LPC_RTC_CTRL_ONSW (1 << 7) +#define LPC_RTC_CTRL_DISABLE (1 << 6) +#define LPC_RTC_CTRL_RTCRESET (1 << 4) +#define LPC_RTC_CTRL_MATCH0ONSW (1 << 3) +#define LPC_RTC_CTRL_MATCH1ONSW (1 << 2) +#define LPC_RTC_CTRL_MATCH1INTR (1 << 1) +#define LPC_RTC_CTRL_MATCH0INTR (1 << 0) +#define LPC_RTC_INTSTAT 0x14 +#define LPC_RTC_KEY 0x18 +#define LPC_RTC_SRAM_BEGIN 0x80 +#define LPC_RTC_SRAM_END 0xff + +/* + * MMC/SD controller. (from UM10326: LPC32x0 User manual, page 436) + */ +#define LPC_SD_POWER 0x8000 +#define LPC_SD_CLOCK 0x8004 +#define LPC_SD_ARGUMENT 0x8008 +#define LPC_SD_COMMAND 0x800c +#define LPC_SD_COMMAND_ENABLE (1 << 10) +#define LPC_SD_COMMAND_PENDING (1 << 9) +#define LPC_SD_COMMAND_INTERRUPT (1 << 8) +#define LPC_SD_COMMAND_LONGRSP (1 << 7) +#define LPC_SD_COMMAND_RESPONSE (1 << 6) +#define LPC_SD_COMMAND_CMDINDEXMASK 0x1f +#define LPC_SD_RESPCMD 0x8010 +#define LPC_SD_RESP0 0x8014 +#define LPC_SD_RESP1 0x8018 +#define LPC_SD_RESP2 0x801c +#define LPC_SD_RESP3 0x8020 +#define LPC_SD_DATATIMER 0x8024 +#define LPC_SD_DATALENGTH 0x8028 +#define LPC_SD_DATACTRL 0x802c +#define LPC_SD_DATACTRL_BLOCKSIZESHIFT 4 +#define LPC_SD_DATACTRL_BLOCKSIZEMASK 0xf +#define LPC_SD_DATACTRL_DMAENABLE (1 << 3) +#define LPC_SD_DATACTRL_MODE (1 << 2) +#define LPC_SD_DATACTRL_DIRECTION (1 << 1) +#define LPC_SD_DATACTRL_ENABLE (1 << 0) +#define LPC_SD_DATACNT 0x8030 +#define LPC_SD_STATUS 0x8034 +#define LPC_SD_STATUS_RXDATAAVLBL (1 << 21) +#define LPC_SD_STATUS_TXDATAAVLBL (1 << 20) +#define LPC_SD_STATUS_RXFIFOEMPTY (1 << 19) +#define LPC_SD_STATUS_TXFIFOEMPTY (1 << 18) +#define LPC_SD_STATUS_RXFIFOFULL (1 << 17) +#define LPC_SD_STATUS_TXFIFOFULL (1 << 16) +#define LPC_SD_STATUS_RXFIFOHALFFULL (1 << 15) +#define LPC_SD_STATUS_TXFIFOHALFEMPTY (1 << 14) +#define LPC_SD_STATUS_RXACTIVE (1 << 13) +#define LPC_SD_STATUS_TXACTIVE (1 << 12) +#define LPC_SD_CLEAR 0x8038 +#define LPC_SD_MASK0 0x803c +#define LPC_SD_MASK1 0x8040 +#define LPC_SD_FIFOCNT 0x8048 +#define LPC_SD_FIFO 0x8080 + +/* + * USB OTG controller (from UM10326: LPC32x0 User manual, page 410) + */ +#define LPC_OTG_INT_STATUS 0x100 +#define LPC_OTG_INT_ENABLE 0x104 +#define LPC_OTG_INT_SET 0x108 +#define LPC_OTG_INT_CLEAR 0x10c +#define LPC_OTG_STATUS 0x110 +#define LPC_OTG_STATUS_ATOB_HNP_TRACK (1 << 9) +#define LPC_OTG_STATUS_BTOA_HNP_TACK (1 << 8) +#define LPC_OTG_STATUS_TRANSP_I2C_EN (1 << 7) +#define LPC_OTG_STATUS_TIMER_RESET (1 << 6) +#define LPC_OTG_STATUS_TIMER_EN (1 << 5) +#define LPC_OTG_STATUS_TIMER_MODE (1 << 4) +#define LPC_OTG_STATUS_TIMER_SCALE (1 << 2) +#define LPC_OTG_STATUS_HOST_EN (1 << 0) +#define LPC_OTG_TIMER 0x114 +#define LPC_OTG_I2C_TXRX 0x300 +#define LPC_OTG_I2C_STATUS 0x304 +#define LPC_OTG_I2C_STATUS_TFE (1 << 11) +#define LPC_OTG_I2C_STATUS_TFF (1 << 10) +#define LPC_OTG_I2C_STATUS_RFE (1 << 9) +#define LPC_OTG_I2C_STATUS_RFF (1 << 8) +#define LPC_OTG_I2C_STATUS_SDA (1 << 7) +#define LPC_OTG_I2C_STATUS_SCL (1 << 6) +#define LPC_OTG_I2C_STATUS_ACTIVE (1 << 5) +#define LPC_OTG_I2C_STATUS_DRSI (1 << 4) +#define LPC_OTG_I2C_STATUS_DRMI (1 << 3) +#define LPC_OTG_I2C_STATUS_NAI (1 << 2) +#define LPC_OTG_I2C_STATUS_AFI (1 << 1) +#define LPC_OTG_I2C_STATUS_TDI (1 << 0) +#define LPC_OTG_I2C_CTRL 0x308 +#define LPC_OTG_I2C_CTRL_SRST (1 << 8) +#define LPC_OTG_I2C_CTRL_TFFIE (1 << 7) +#define LPC_OTG_I2C_CTRL_RFDAIE (1 << 6) +#define LPC_OTG_I2C_CTRL_RFFIE (1 << 5) +#define LPC_OTG_I2C_CTRL_DRSIE (1 << 4) +#define LPC_OTG_I2C_CTRL_DRMIE (1 << 3) +#define LPC_OTG_I2C_CTRL_NAIE (1 << 2) +#define LPC_OTG_I2C_CTRL_AFIE (1 << 1) +#define LPC_OTG_I2C_CTRL_TDIE (1 << 0) +#define LPC_OTG_I2C_CLKHI 0x30c +#define LPC_OTG_I2C_CLKLO 0x310 +#define LPC_OTG_CLOCK_CTRL 0xff4 +#define LPC_OTG_CLOCK_CTRL_AHB_EN (1 << 4) +#define LPC_OTG_CLOCK_CTRL_OTG_EN (1 << 3) +#define LPC_OTG_CLOCK_CTRL_I2C_EN (1 << 2) +#define LPC_OTG_CLOCK_CTRL_DEV_EN (1 << 1) +#define LPC_OTG_CLOCK_CTRL_HOST_EN (1 << 0) +#define LPC_OTG_CLOCK_STATUS 0xff8 + +/* + * ISP3101 USB transceiver registers + */ +#define LPC_ISP3101_I2C_ADDR 0x2d +#define LPC_ISP3101_MODE_CONTROL_1 0x04 +#define LPC_ISP3101_MC1_SPEED_REG (1 << 0) +#define LPC_ISP3101_MC1_SUSPEND_REG (1 << 1) +#define LPC_ISP3101_MC1_DAT_SE0 (1 << 2) +#define LPC_ISP3101_MC1_TRANSPARENT (1 << 3) +#define LPC_ISP3101_MC1_BDIS_ACON_EN (1 << 4) +#define LPC_ISP3101_MC1_OE_INT_EN (1 << 5) +#define LPC_ISP3101_MC1_UART_EN (1 << 6) +#define LPC_ISP3101_MODE_CONTROL_2 0x12 +#define LPC_ISP3101_MC2_GLOBAL_PWR_DN (1 << 0) +#define LPC_ISP3101_MC2_SPD_SUSP_CTRL (1 << 1) +#define LPC_ISP3101_MC2_BI_DI (1 << 2) +#define LPC_ISP3101_MC2_TRANSP_BDIR0 (1 << 3) +#define LPC_ISP3101_MC2_TRANSP_BDIR1 (1 << 4) +#define LPC_ISP3101_MC2_AUDIO_EN (1 << 5) +#define LPC_ISP3101_MC2_PSW_EN (1 << 6) +#define LPC_ISP3101_MC2_EN2V7 (1 << 7) +#define LPC_ISP3101_OTG_CONTROL_1 0x06 +#define LPC_ISP3101_OTG1_DP_PULLUP (1 << 0) +#define LPC_ISP3101_OTG1_DM_PULLUP (1 << 1) +#define LPC_ISP3101_OTG1_DP_PULLDOWN (1 << 2) +#define LPC_ISP3101_OTG1_DM_PULLDOWN (1 << 3) +#define LPC_ISP3101_OTG1_ID_PULLDOWN (1 << 4) +#define LPC_ISP3101_OTG1_VBUS_DRV (1 << 5) +#define LPC_ISP3101_OTG1_VBUS_DISCHRG (1 << 6) +#define LPC_ISP3101_OTG1_VBUS_CHRG (1 << 7) +#define LPC_ISP3101_OTG_CONTROL_2 0x10 +#define LPC_ISP3101_OTG_INTR_LATCH 0x0a +#define LPC_ISP3101_OTG_INTR_FALLING 0x0c +#define LPC_ISP3101_OTG_INTR_RISING 0x0e +#define LPC_ISP3101_REG_CLEAR_ADDR 0x01 + #endif /* _ARM_LPC_LPCREG_H */ ==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpcvar.h#2 (text+ko) ==== @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2010 Semihalf, Jakub Klama + * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org> * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -24,31 +24,14 @@ * SUCH DAMAGE. */ -#ifndef _ARM_DAVINCI_DAVINCIVAR_H -#define _ARM_DAVINCI_DAVINCIVAR_H +#ifndef _ARM_LPC_LPCVAR_H +#define _ARM_LPC_LPCVAR_H #include <sys/types.h> #include <sys/bus.h> #include <machine/bus.h> -struct obio_device { - const char * od_name; - u_long od_base; - u_long od_size; - int od_irqs[7]; - /* PSC controller module numbers */ - int od_psc[7]; - /* EDMA channel numbers */ - int od_edma[7]; -}; +uint32_t lpc_pwr_read(device_t, int); +void lpc_pwr_write(device_t, int, uint32_t); -#define DAVINCI_SYSCLK1 1 -#define DAVINCI_SYSCLK2 2 -#define DAVINCI_SYSCLK3 3 -#define DAVINCI_SYSCLK5 5 -uint32_t davinci_sysclk(int); - -extern struct obio_device davinci_devices[]; -extern bus_space_tag_t obio_tag; - -#endif /* _ARM_DAVINCI_DAVINCIVAR_H */ +#endif /* _ARM_LPC_LPCVAR_H */ ==== //depot/projects/soc2011/jceel_lpc/sys/boot/fdt/dts/ea3250.dts#4 (text+ko) ====
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