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Date:      Fri, 7 Mar 2014 17:21:11 +0200
From:      Konstantin Belousov <kostikbel@gmail.com>
To:        Ian Lepore <ian@FreeBSD.org>
Cc:        svn-src-head@FreeBSD.org, svn-src-all@FreeBSD.org, src-committers@FreeBSD.org
Subject:   Re: svn commit: r262411 - head/sys/arm/arm
Message-ID:  <20140307152111.GL24664@kib.kiev.ua>
In-Reply-To: <1394025767.1149.327.camel@revolution.hippie.lan>
References:  <201402232252.s1NMqmI5075701@svn.freebsd.org> <20140305115402.GC24664@kib.kiev.ua> <1394025767.1149.327.camel@revolution.hippie.lan>

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On Wed, Mar 05, 2014 at 06:22:47AM -0700, Ian Lepore wrote:
> On Wed, 2014-03-05 at 13:54 +0200, Konstantin Belousov wrote:
> > On Sun, Feb 23, 2014 at 10:52:48PM +0000, Ian Lepore wrote:
> > > Author: ian
> > > Date: Sun Feb 23 22:52:48 2014
> > > New Revision: 262411
> > > URL: http://svnweb.freebsd.org/changeset/base/262411
> > >=20
> > > Log:
> > >   If the L2 cache type is PIPT, pass a physical address for a flush.
> > >  =20
> > >   While this is technically more correct, I don't think it much matte=
rs,
> > >   because the only thing in the tree that calls cpu_flush_dcache() is=
 md(4)
> > >   and I'm > 99% sure it's bogus that it does so; md has no ability to=
 do
> > >   anything that can perturb data cache coherency.
> >=20
> > Yes, md(4) does not break data cache coherency, but I think that
> > Marcel added the flush to ensure instruction cache coherency.  The
> > intent was to ensure that harward-architecture machines would
> > see up-to-date memory content when fetching instructions after
> > read on md(4).
>=20
> Oh.  If that's necessary on ia64, it seems like ia64/elf_machdep.c would
> be the place to do the flush.

I am not sure about ia64, it was needed for PowerPC, I think.
The issue is not limited to the module loads, so elf_machdep.c cannot
solve the problem.

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