Date: Mon, 15 Nov 2021 15:22:55 GMT From: Mitchell Horne <mhorne@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: c8a4404da737 - stable/12 - hwpmc: initialize arm64 counter/interrupt state Message-ID: <202111151522.1AFFMtsf012937@gitrepo.freebsd.org>
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The branch stable/12 has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=c8a4404da737ea7e859287094de38953a84bdd68 commit c8a4404da737ea7e859287094de38953a84bdd68 Author: Mitchell Horne <mhorne@FreeBSD.org> AuthorDate: 2021-11-08 19:33:25 +0000 Commit: Mitchell Horne <mhorne@FreeBSD.org> CommitDate: 2021-11-15 15:22:35 +0000 hwpmc: initialize arm64 counter/interrupt state Performance counters and overflow interrupts are assumed to be disabled by default, but this is not guaranteed. Ensure we disable both during per-cpu initialization, before enabling the PMU. Otherwise, some systems (such as the Ampere eMAG) would experience an interrupt storm upon loading the hwpmc module. Reviewed by: br MFC after: 5 days Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D32854 (cherry picked from commit b826cc3caf6abc6a5d1926bd478b464938d45697) --- sys/dev/hwpmc/hwpmc_arm64.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/sys/dev/hwpmc/hwpmc_arm64.c b/sys/dev/hwpmc/hwpmc_arm64.c index af028d3fce94..919f588afff2 100644 --- a/sys/dev/hwpmc/hwpmc_arm64.c +++ b/sys/dev/hwpmc/hwpmc_arm64.c @@ -454,6 +454,16 @@ arm64_pcpu_init(struct pmc_mdep *md, int cpu) pc->pc_hwpmcs[i + first_ri] = phw; } + /* + * Disable all counters and overflow interrupts. Upon reset they are in + * an undefined state. + * + * Don't issue an isb here, just wait for the one in arm64_pmcr_write() + * to make the writes visible. + */ + WRITE_SPECIALREG(pmcntenclr_el0, 0xffffffff); + WRITE_SPECIALREG(pmintenclr_el1, 0xffffffff); + /* Enable unit */ pmcr = arm64_pmcr_read(); pmcr |= PMCR_E;
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