Date: Fri, 5 Jan 2018 09:39:50 +0000 From: David Chisnall <theraven@FreeBSD.org> To: Jon Brawn <jon@brawn.org> Cc: Nathan Whitehorn <nwhitehorn@freebsd.org>, freebsd-current@freebsd.org Subject: Re: Programmatically cache line Message-ID: <1F3E7B40-1166-4045-AB9D-17D6FD70362F@FreeBSD.org> In-Reply-To: <E6012938-FE63-4459-AAE8-3B469CF18611@brawn.org> References: <CALM2mEmWYz5nyqvxMJwMWoFOXnDTvWFrEug7UUha6xe7Um6ODw@mail.gmail.com> <20171230082812.GL1684@kib.kiev.ua> <CAJ-VmomxGJsn8eOtWoqevdW-spUPgcSGKEc7eR4xuXLP-E1XRA@mail.gmail.com> <08038E36-9679-4286-9083-FCEDD637ADCC@FreeBSD.org> <20180101103655.GF1684@kib.kiev.ua> <CABh_MK=2uvPoNCg7qL14yVuxo_%2BHVSvccLTBAnRAHNzqor--0g@mail.gmail.com> <35d2d373-92f1-499f-f470-e4528b08b937@freebsd.org> <71E8D6E7-F833-4B7E-B1F1-AD07A49CAF98@FreeBSD.org> <E6012938-FE63-4459-AAE8-3B469CF18611@brawn.org>
index | next in thread | previous in thread | raw e-mail
On 5 Jan 2018, at 02:46, Jon Brawn <jon@brawn.org> wrote: > This idea of Arm big.LITTLE systems having cache lines of different lengths really, really bothers me - how on earth is the cache coherency supposed to work in such a system? I doubt the usual cache coherency protocols would work - probably need a really MESSY protocol to deal with this config :-) I believe that the systems that have different cache line sizes (which ARM explicitly tells partners not to do) don’t allow cores from both the big and little clusters to be active at the same time - the OS is supposed to migrate everything entirely from one cluster to the other. The more complex designs, that allow mixes of cores from two or three different clusters that I’m aware of all have the same cache line size. Davidhelp
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?1F3E7B40-1166-4045-AB9D-17D6FD70362F>