Date: Mon, 17 Feb 2014 02:24:58 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r262010 - head/sys/dev/etherswitch/arswitch Message-ID: <201402170224.s1H2Owv8085127@svn.freebsd.org>
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Author: adrian Date: Mon Feb 17 02:24:58 2014 New Revision: 262010 URL: http://svnweb.freebsd.org/changeset/base/262010 Log: Implement PHY bus MMD writes for arswitch. This is used by the AR8327 PHY setup path. Obtained from: OpenWRT Modified: head/sys/dev/etherswitch/arswitch/arswitch_reg.c head/sys/dev/etherswitch/arswitch/arswitchreg.h Modified: head/sys/dev/etherswitch/arswitch/arswitch_reg.c ============================================================================== --- head/sys/dev/etherswitch/arswitch/arswitch_reg.c Mon Feb 17 01:40:33 2014 (r262009) +++ head/sys/dev/etherswitch/arswitch/arswitch_reg.c Mon Feb 17 02:24:58 2014 (r262010) @@ -111,6 +111,16 @@ arswitch_writedbg(device_t dev, int phy, MII_ATH_DBG_DATA, dbg_data); } +void +arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr, + uint16_t dbg_data) +{ + (void) MDIO_WRITEREG(device_get_parent(dev), phy, + MII_ATH_MMD_ADDR, dbg_addr); + (void) MDIO_WRITEREG(device_get_parent(dev), phy, + MII_ATH_MMD_DATA, dbg_data); +} + /* * Write half a register */ Modified: head/sys/dev/etherswitch/arswitch/arswitchreg.h ============================================================================== --- head/sys/dev/etherswitch/arswitch/arswitchreg.h Mon Feb 17 01:40:33 2014 (r262009) +++ head/sys/dev/etherswitch/arswitch/arswitchreg.h Mon Feb 17 02:24:58 2014 (r262010) @@ -39,6 +39,8 @@ #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) /* Atheros specific MII registers */ +#define MII_ATH_MMD_ADDR 0x0d +#define MII_ATH_MMD_DATA 0x0e #define MII_ATH_DBG_ADDR 0x1d #define MII_ATH_DBG_DATA 0x1e
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