Date: Mon, 15 Sep 2025 19:21:47 GMT From: Mitchell Horne <mhorne@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: 4efc1b22aab1 - stable/14 - riscv: Fix SSTC extension support Message-ID: <202509151921.58FJLlHh073275@gitrepo.freebsd.org>
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The branch stable/14 has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=4efc1b22aab1a15bff95012deb789696d71f97ec commit 4efc1b22aab1a15bff95012deb789696d71f97ec Author: Ruslan Bukin <br@FreeBSD.org> AuthorDate: 2024-05-22 14:51:45 +0000 Commit: Mitchell Horne <mhorne@FreeBSD.org> CommitDate: 2025-09-15 19:20:27 +0000 riscv: Fix SSTC extension support From the SSTC spec: "If the stimecmp (supervisor-mode timer compare) register is implemented, then STIP is read-only in mip and reflects the supervisor-level timer interrupt signal resulting from stimecmp. This timer interrupt signal is cleared by writing stimecmp with a value greater than the current time value." This fixes operation in Spike with sstc extension enabled. Example: spike --isa RV64IMAFDCH_zicntr_zihpm_sstc Reviewed by: mhorne Differential Revision: https://reviews.freebsd.org/D45226 (cherry picked from commit ddd0d4f4cd65341a07bb3bb833dee7982018fd60) --- sys/riscv/riscv/timer.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/sys/riscv/riscv/timer.c b/sys/riscv/riscv/timer.c index e3d7fc87cea2..b4aa054cae9d 100644 --- a/sys/riscv/riscv/timer.c +++ b/sys/riscv/riscv/timer.c @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> + * Copyright (c) 2015-2024 Ruslan Bukin <br@bsdpad.com> * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -144,7 +144,10 @@ riscv_timer_intr(void *arg) sc = (struct riscv_timer_softc *)arg; - csr_clear(sip, SIP_STIP); + if (has_sstc) + csr_write(stimecmp, -1UL); + else + csr_clear(sip, SIP_STIP); if (sc->et.et_active) sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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