Date: Wed, 15 May 2002 03:30:06 -0700 (PDT) From: Thomas Nystrom <thn@saeab.se> To: freebsd-bugs@FreeBSD.org Subject: Re: kern/37929: hang of vr interface running at 100 MBit/full duples Message-ID: <200205151030.g4FAU6f98079@freefall.freebsd.org>
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The following reply was made to PR kern/37929; it has been noted by GNATS. From: Thomas Nystrom <thn@saeab.se> To: freebsd-gnats-submit@FreeBSD.org, thn@saeab.se Cc: Subject: Re: kern/37929: hang of vr interface running at 100 MBit/full duples Date: Wed, 15 May 2002 12:25:44 +0200 This is a multi-part message in MIME format. --------------E50CD34C1BFFA3B64FEC3D14 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit The problem is solved by the attached patches. In the documentation for the VT6102 chip it could be found that there are two different registers each to set the TXFIFO and RXFIFO threshold. The driver only sets one of theese registers but the other non-initialized register have higher priority. The patches initialize both registers (changes to both if_vr.c and the register definitions in if_vrreg.h). Both patches are relative to the files included in 4.5-RELEASE. /thn --------------E50CD34C1BFFA3B64FEC3D14 Content-Type: text/plain; charset=us-ascii; name="if_vr.c.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="if_vr.c.diff" --- /usr/FreeBSD/4.5/disk/usr/src/sys/pci/if_vr.c Sun Dec 16 16:46:08 2001 +++ if_vr.c Wed May 15 11:56:32 2002 @@ -1402,6 +1402,13 @@ for (i = 0; i < ETHER_ADDR_LEN; i++) CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); + /* VT6102 have two registers to set threshholds, set both */ + VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); + VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESHSTORENFWD); + + VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); + VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); + VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); --------------E50CD34C1BFFA3B64FEC3D14 Content-Type: text/plain; charset=us-ascii; name="if_vrreg.h.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="if_vrreg.h.diff" --- /usr/FreeBSD/4.5/disk/usr/src/sys/pci/if_vrreg.h Mon May 14 21:13:43 2001 +++ if_vrreg.h Wed May 15 10:52:05 2002 @@ -278,6 +278,46 @@ #define VR_STICKHW_LEGWOL_ENB 0x80 /* + * BCR0 register bits. (At least for the VT6102 chip.) + */ +#define VR_BCR0_DMA_LENGTH 0x07 + +#define VR_BCR0_DMA_32BYTES 0x00 +#define VR_BCR0_DMA_64BYTES 0x01 +#define VR_BCR0_DMA_128BYTES 0x02 +#define VR_BCR0_DMA_256BYTES 0x03 +#define VR_BCR0_DMA_512BYTES 0x04 +#define VR_BCR0_DMA_1024BYTES 0x05 +#define VR_BCR0_DMA_STORENFWD 0x07 + +#define VR_BCR0_RX_THRESH 0x38 + +#define VR_BCR0_RXTHRESHCFG 0x00 +#define VR_BCR0_RXTHRESH64BYTES 0x08 +#define VR_BCR0_RXTHRESH128BYTES 0x10 +#define VR_BCR0_RXTHRESH256BYTES 0x18 +#define VR_BCR0_RXTHRESH512BYTES 0x20 +#define VR_BCR0_RXTHRESH1024BYTES 0x28 +#define VR_BCR0_RXTHRESHSTORENFWD 0x38 +#define VR_BCR0_EXTLED 0x40 +#define VR_BCR0_MED2 0x80 + +/* + * BCR1 register bits. (At least for the VT6102 chip.) + */ +#define VR_BCR1_POT0 0x01 +#define VR_BCR1_POT1 0x02 +#define VR_BCR1_POT2 0x04 +#define VR_BCR1_TX_THRESH 0x38 +#define VR_BCR1_TXTHRESHCFG 0x00 +#define VR_BCR1_TXTHRESH64BYTES 0x08 +#define VR_BCR1_TXTHRESH128BYTES 0x10 +#define VR_BCR1_TXTHRESH256BYTES 0x18 +#define VR_BCR1_TXTHRESH512BYTES 0x20 +#define VR_BCR1_TXTHRESH1024BYTES 0x28 +#define VR_BCR1_TXTHRESHSTORENFWD 0x38 + +/* * Rhine TX/RX list structure. */ --------------E50CD34C1BFFA3B64FEC3D14-- To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-bugs" in the body of the message
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