Date: Thu, 23 Oct 1997 02:55:29 -0700 From: Don Lewis <Don.Lewis@tsc.tdk.com> To: Charles Henrich <henrich@crh.cl.msu.edu>, freebsd-hackers@FreeBSD.ORG Subject: Re: de0 errors Message-ID: <199710230955.CAA13696@salsa.gv.tsc.tdk.com> In-Reply-To: Charles Henrich <henrich@crh.cl.msu.edu> "de0 errors" (Oct 23, 12:57am)
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On Oct 23, 12:57am, Charles Henrich wrote: } Subject: de0 errors } After moving to 2.2.5-RELEASE im seeing: } } Oct 23 00:32:12 msunews /kernel: ccd0-3: Concatenated disk drivers } Oct 23 00:35:45 msunews /kernel: de0: abnormal interrupt: transmit underflow } (raising TX threshold to 96|256) } Oct 23 00:36:01 msunews /kernel: de0: abnormal interrupt: transmit underflow } (raising TX threshold to 8|512) } Oct 23 00:37:41 msunews /kernel: de0: abnormal interrupt: transmit underflow } (raising TX threshold to 1024) } Oct 23 00:55:14 msunews /kernel: de0: abnormal interrupt: transmit underflow } (switching to store-and-forward mode) The 2114x chips have an internal FIFO into which they load transmit data before sending the packet. To cut down on latency and increase performance, they don't require that the entire packet be loaded into the FIFO before starting transmission. There are a couple of bits in a control register to tell the 2114x how much data to load before starting, and their meaning is adjusted by another control bit that is supposed to indicate the transmission speed that adjusts the values. In 10Mb mode, the threshold values before transmission starts are 72, 96, 128, and 160 bytes. In 100Mb mode, the values are 128, 256, 512, and 1024 bytes. The threshold has to be set large enough so that the 2114x won't run out of data to transmit even if there are delays in transferring data across the PCI bus, since you can't pause the transmission of a packet to wait for the rest of the data to arrive. Since the FIFO drains faster at 100Mb, the threshold values are larger in that mode. There's also another control bit to force the 2114x to load the entire packet into the FIFO before starting to transmit, which will guarantee that it won't run out of data. Depending on the card, it is possible for the PHY chip to automatically sense the network speed so that it can communicate with the network. This will automatically set the data rate into and out of the 2114x. Since there are so many different variations of 2114x-based cards the driver may not be able to always correctly detect the speed the card is running at and may incorrectly set the network speed bit in the 2114x. If the card is connected to a 100Mb network but the driver thinks it's only 10Mb, the transmit threshold values will be to small and the FIFO will empty of data in the middle of a packet. The messages you see are this sort of underflow occuring. The four transmit underflows that you see indicate that four corrupted packets have been sent, which the driver detected and compensated for. Once the driver configures the store-and-forward mode, no more corrupted packets will be sent, but your card may not be operating as efficiently as possible. What speed is your network (10Mb or 100Mb)? What speed does the de driver think it's running at? What kind of card do you have? The other possibility is excessive delays in copying data across the PCI bus. This could indicate a configuration problem, like the latency timer values being mis-programmed.
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