Date: Mon, 15 Sep 2025 19:21:48 GMT From: Mitchell Horne <mhorne@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: 31eaa0141c49 - stable/14 - riscv timer: fix interrupt handling. Message-ID: <202509151921.58FJLmgZ073315@gitrepo.freebsd.org>
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The branch stable/14 has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=31eaa0141c49128fabfc65f3d282997a8d5e9cdc commit 31eaa0141c49128fabfc65f3d282997a8d5e9cdc Author: Ruslan Bukin <br@FreeBSD.org> AuthorDate: 2025-03-26 08:09:50 +0000 Commit: Mitchell Horne <mhorne@FreeBSD.org> CommitDate: 2025-09-15 19:20:32 +0000 riscv timer: fix interrupt handling. Based on the spec the STIP bit of SIP register is read-only. To clear STIP bit from supervisor we have to do an SBI call to firmware. Upon reception of SBI request, the machine-mode firmware clears the STIP bit in the MIP register. This fixes operation on Codasip A730. Reviewed by: mhorne Differential Revision: https://reviews.freebsd.org/D49487 (cherry picked from commit 6d58c670060a17817fa0c8ebf4e7543c3d2b4523) --- sys/riscv/riscv/timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/riscv/riscv/timer.c b/sys/riscv/riscv/timer.c index b4aa054cae9d..8390fa9c448c 100644 --- a/sys/riscv/riscv/timer.c +++ b/sys/riscv/riscv/timer.c @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2015-2024 Ruslan Bukin <br@bsdpad.com> + * Copyright (c) 2015-2025 Ruslan Bukin <br@bsdpad.com> * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -147,7 +147,7 @@ riscv_timer_intr(void *arg) if (has_sstc) csr_write(stimecmp, -1UL); else - csr_clear(sip, SIP_STIP); + sbi_set_timer(-1UL); if (sc->et.et_active) sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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