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Date:      Wed, 30 Oct 2019 12:47:00 +0000 (UTC)
From:      Andrew Turner <andrew@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r354177 - in head/sys: arm64/arm64 dev/hwpmc
Message-ID:  <201910301247.x9UCl01w096599@repo.freebsd.org>
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Author: andrew
Date: Wed Oct 30 12:47:00 2019
New Revision: 354177
URL: https://svnweb.freebsd.org/changeset/base/354177

Log:
  Use a lowercase name for arm64 special registers so they don't conflict
  with macros of the same name.
  
  Sponsored by:	DARPA, AFRL

Modified:
  head/sys/arm64/arm64/debug_monitor.c
  head/sys/arm64/arm64/freebsd32_machdep.c
  head/sys/arm64/arm64/gic_v3_reg.h
  head/sys/arm64/arm64/machdep.c
  head/sys/arm64/arm64/trap.c
  head/sys/dev/hwpmc/hwpmc_arm64.c

Modified: head/sys/arm64/arm64/debug_monitor.c
==============================================================================
--- head/sys/arm64/arm64/debug_monitor.c	Wed Oct 30 12:33:36 2019	(r354176)
+++ head/sys/arm64/arm64/debug_monitor.c	Wed Oct 30 12:47:00 2019	(r354177)
@@ -468,8 +468,8 @@ dbg_monitor_init(void)
 	u_int i;
 
 	/* Find out many breakpoints and watchpoints we can use */
-	dbg_watchpoint_num = ((READ_SPECIALREG(ID_AA64DFR0_EL1) >> 20) & 0xf) + 1;
-	dbg_breakpoint_num = ((READ_SPECIALREG(ID_AA64DFR0_EL1) >> 12) & 0xf) + 1;
+	dbg_watchpoint_num = ((READ_SPECIALREG(id_aa64dfr0_el1) >> 20) & 0xf) + 1;
+	dbg_breakpoint_num = ((READ_SPECIALREG(id_aa64dfr0_el1) >> 12) & 0xf) + 1;
 
 	if (bootverbose && PCPU_GET(cpuid) == 0) {
 		printf("%d watchpoints and %d breakpoints supported\n",

Modified: head/sys/arm64/arm64/freebsd32_machdep.c
==============================================================================
--- head/sys/arm64/arm64/freebsd32_machdep.c	Wed Oct 30 12:33:36 2019	(r354176)
+++ head/sys/arm64/arm64/freebsd32_machdep.c	Wed Oct 30 12:47:00 2019	(r354177)
@@ -72,8 +72,8 @@ freebsd32_sysarch(struct thread *td, struct freebsd32_
 
 	switch(uap->op) {
 	case ARM_SET_TP:
-		WRITE_SPECIALREG(TPIDR_EL0, uap->parms);
-		WRITE_SPECIALREG(TPIDRRO_EL0, uap->parms);
+		WRITE_SPECIALREG(tpidr_el0, uap->parms);
+		WRITE_SPECIALREG(tpidrro_el0, uap->parms);
 		return 0;
 	case ARM_SYNC_ICACHE:
 		{

Modified: head/sys/arm64/arm64/gic_v3_reg.h
==============================================================================
--- head/sys/arm64/arm64/gic_v3_reg.h	Wed Oct 30 12:33:36 2019	(r354176)
+++ head/sys/arm64/arm64/gic_v3_reg.h	Wed Oct 30 12:47:00 2019	(r354177)
@@ -389,7 +389,7 @@
 
 #define	gic_icc_write(reg, val)					\
 do {								\
-	WRITE_SPECIALREG(ICC_ ##reg ##_EL1, val);		\
+	WRITE_SPECIALREG(icc_ ##reg ##_el1, val);		\
 	isb();							\
 } while (0)
 
@@ -397,7 +397,7 @@ do {								\
 ({								\
 	uint64_t val;						\
 								\
-	val = READ_SPECIALREG(ICC_ ##reg ##_EL1);		\
+	val = READ_SPECIALREG(icc_ ##reg ##_el1);		\
 	(val);							\
 })
 

Modified: head/sys/arm64/arm64/machdep.c
==============================================================================
--- head/sys/arm64/arm64/machdep.c	Wed Oct 30 12:33:36 2019	(r354176)
+++ head/sys/arm64/arm64/machdep.c	Wed Oct 30 12:47:00 2019	(r354177)
@@ -1150,7 +1150,7 @@ dbg_init(void)
 {
 
 	/* Clear OS lock */
-	WRITE_SPECIALREG(OSLAR_EL1, 0);
+	WRITE_SPECIALREG(oslar_el1, 0);
 
 	/* This permits DDB to use debug registers for watchpoints. */
 	dbg_monitor_init();

Modified: head/sys/arm64/arm64/trap.c
==============================================================================
--- head/sys/arm64/arm64/trap.c	Wed Oct 30 12:33:36 2019	(r354176)
+++ head/sys/arm64/arm64/trap.c	Wed Oct 30 12:47:00 2019	(r354177)
@@ -480,8 +480,8 @@ do_el0_sync(struct thread *td, struct trapframe *frame
 	case EXCP_SOFTSTP_EL0:
 		td->td_frame->tf_spsr &= ~PSR_SS;
 		td->td_pcb->pcb_flags &= ~PCB_SINGLE_STEP;
-		WRITE_SPECIALREG(MDSCR_EL1,
-		    READ_SPECIALREG(MDSCR_EL1) & ~DBG_MDSCR_SS);
+		WRITE_SPECIALREG(mdscr_el1,
+		    READ_SPECIALREG(mdscr_el1) & ~DBG_MDSCR_SS);
 		call_trapsignal(td, SIGTRAP, TRAP_TRACE,
 		    (void *)frame->tf_elr);
 		userret(td, frame);

Modified: head/sys/dev/hwpmc/hwpmc_arm64.c
==============================================================================
--- head/sys/dev/hwpmc/hwpmc_arm64.c	Wed Oct 30 12:33:36 2019	(r354176)
+++ head/sys/dev/hwpmc/hwpmc_arm64.c	Wed Oct 30 12:47:00 2019	(r354177)
@@ -63,7 +63,7 @@ arm64_interrupt_enable(uint32_t pmc)
 	uint32_t reg;
 
 	reg = (1 << pmc);
-	WRITE_SPECIALREG(PMINTENSET_EL1, reg);
+	WRITE_SPECIALREG(pmintenset_el1, reg);
 
 	isb();
 }
@@ -77,7 +77,7 @@ arm64_interrupt_disable(uint32_t pmc)
 	uint32_t reg;
 
 	reg = (1 << pmc);
-	WRITE_SPECIALREG(PMINTENCLR_EL1, reg);
+	WRITE_SPECIALREG(pmintenclr_el1, reg);
 
 	isb();
 }
@@ -91,7 +91,7 @@ arm64_counter_enable(unsigned int pmc)
 	uint32_t reg;
 
 	reg = (1 << pmc);
-	WRITE_SPECIALREG(PMCNTENSET_EL0, reg);
+	WRITE_SPECIALREG(pmcntenset_el0, reg);
 
 	isb();
 }
@@ -105,7 +105,7 @@ arm64_counter_disable(unsigned int pmc)
 	uint32_t reg;
 
 	reg = (1 << pmc);
-	WRITE_SPECIALREG(PMCNTENCLR_EL0, reg);
+	WRITE_SPECIALREG(pmcntenclr_el0, reg);
 
 	isb();
 }
@@ -118,7 +118,7 @@ arm64_pmcr_read(void)
 {
 	uint32_t reg;
 
-	reg = READ_SPECIALREG(PMCR_EL0);
+	reg = READ_SPECIALREG(pmcr_el0);
 
 	return (reg);
 }
@@ -127,7 +127,7 @@ static void
 arm64_pmcr_write(uint32_t reg)
 {
 
-	WRITE_SPECIALREG(PMCR_EL0, reg);
+	WRITE_SPECIALREG(pmcr_el0, reg);
 
 	isb();
 }
@@ -141,11 +141,11 @@ arm64_pmcn_read(unsigned int pmc)
 
 	KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
 
-	WRITE_SPECIALREG(PMSELR_EL0, pmc);
+	WRITE_SPECIALREG(pmselr_el0, pmc);
 
 	isb();
 
-	return (READ_SPECIALREG(PMXEVCNTR_EL0));
+	return (READ_SPECIALREG(pmxevcntr_el0));
 }
 
 static void
@@ -154,8 +154,8 @@ arm64_pmcn_write(unsigned int pmc, uint32_t reg)
 
 	KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
 
-	WRITE_SPECIALREG(PMSELR_EL0, pmc);
-	WRITE_SPECIALREG(PMXEVCNTR_EL0, reg);
+	WRITE_SPECIALREG(pmselr_el0, pmc);
+	WRITE_SPECIALREG(pmxevcntr_el0, reg);
 
 	isb();
 }
@@ -273,8 +273,8 @@ arm64_start_pmc(int cpu, int ri)
 	/*
 	 * Configure the event selection.
 	 */
-	WRITE_SPECIALREG(PMSELR_EL0, ri);
-	WRITE_SPECIALREG(PMXEVTYPER_EL0, config);
+	WRITE_SPECIALREG(pmselr_el0, ri);
+	WRITE_SPECIALREG(pmxevtyper_el0, config);
 
 	isb();
 
@@ -347,10 +347,10 @@ arm64_intr(struct trapframe *tf)
 
 		/* Check if counter is overflowed */
 		reg = (1 << ri);
-		if ((READ_SPECIALREG(PMOVSCLR_EL0) & reg) == 0)
+		if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0)
 			continue;
 		/* Clear Overflow Flag */
-		WRITE_SPECIALREG(PMOVSCLR_EL0, reg);
+		WRITE_SPECIALREG(pmovsclr_el0, reg);
 
 		isb();

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