Date: Wed, 28 May 2025 13:35:07 GMT From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 33ec71d6c0e9 - main - arm64: Add more PMCR_EL0 fields Message-ID: <202505281335.54SDZ7t3017699@gitrepo.freebsd.org>
next in thread | raw e-mail | index | archive | help
The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=33ec71d6c0e93cde6132c4d811d8a88188203c29 commit 33ec71d6c0e93cde6132c4d811d8a88188203c29 Author: Andrew Turner <andrew@FreeBSD.org> AuthorDate: 2025-05-27 19:55:21 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2025-05-27 19:55:21 +0000 arm64: Add more PMCR_EL0 fields Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D50430 --- sys/arm64/include/armreg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 1571fe273e16..33866d7f822b 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -2377,6 +2377,8 @@ #define PMCR_X (1ul << 4) /* Export to ext. monitoring (ETM) */ #define PMCR_DP (1ul << 5) /* Disable CCNT if non-invasive debug*/ #define PMCR_LC (1ul << 6) /* Long cycle count enable */ +#define PMCR_LP (1ul << 7) /* Long event count enable */ +#define PMCR_FZO (1ul << 9) /* Freeze-on-overflow */ #define PMCR_N_SHIFT 11 /* Number of counters implemented */ #define PMCR_N_MASK (0x1ful << PMCR_N_SHIFT) #define PMCR_IDCODE_SHIFT 16 /* Identification code */ @@ -2395,6 +2397,7 @@ #define PMCR_IMP_SHIFT 24 /* Implementer code */ #define PMCR_IMP_MASK (0xfful << PMCR_IMP_SHIFT) #define PMCR_IMP_ARM 0x41 +#define PMCR_FZS (1ul << 32) /* Freeze-on-SPE event */ /* PMEVCNTR<n>_EL0 */ #define PMEVCNTR_EL0_op0 3
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?202505281335.54SDZ7t3017699>