Date: Fri, 09 Jan 1998 23:01:19 +1030 From: Mike Smith <mike@smith.net.au> To: Greg Lehey <grog@lemis.com> Cc: Mike Smith <mike@smith.net.au>, hardware@FreeBSD.ORG Subject: Re: LS-120, Riva 128, ASUS motherboard Message-ID: <199801091231.XAA00367@word.smith.net.au> In-Reply-To: Your message of "Fri, 09 Jan 1998 19:40:06 %2B1030." <19980109194006.42229@lemis.com>
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> Ahh. http://www.intel.com/design/pcisets/datashts/290559.htm. > Extract: > > The Intel 430TX PCIset (430TX) consists of the 82439TX System > Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator > (PIIX4). [...] The MTXC integrates the cache and main memory DRAM > control functions and provides bus control to transfers between the > CPU, cache, main memory, and the PCI Bus. The second level (L2) > cache controller supports a writeback cache policy for cache sizes > of 256 Kbytes and 512 Kbytes. > > I'm downloading the document, and will print it out, but this > certainly doesn't sound like Tom's Hardware Guide. As is typical, reading the datasheets tends to give better and more believable answers than what is really the computing equivalent of a revhead's magazine. Of course, lightly editorial dreck is easier on the eyes when it comes to reading... -- \\ Sometimes you're ahead, \\ Mike Smith \\ sometimes you're behind. \\ mike@smith.net.au \\ The race is long, and in the \\ msmith@freebsd.org \\ end it's only with yourself. \\
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