Date: Mon, 9 Jul 2012 10:39:57 +0000 (UTC) From: "Jayachandran C." <jchandra@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r238293 - in head/sys/mips/nlm: dev/net hal Message-ID: <201207091039.q69AdvJn011520@svn.freebsd.org>
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Author: jchandra Date: Mon Jul 9 10:39:57 2012 New Revision: 238293 URL: http://svn.freebsd.org/changeset/base/238293 Log: Support Netlogic XLP 8xx B1 revisions in xlpge. Updates to the MDIO access code for the new revision of the XLP chip. Modified: head/sys/mips/nlm/dev/net/mdio.c head/sys/mips/nlm/hal/mdio.h Modified: head/sys/mips/nlm/dev/net/mdio.c ============================================================================== --- head/sys/mips/nlm/dev/net/mdio.c Mon Jul 9 10:36:43 2012 (r238292) +++ head/sys/mips/nlm/dev/net/mdio.c Mon Jul 9 10:39:57 2012 (r238293) @@ -38,6 +38,8 @@ __FBSDID("$FreeBSD$"); #include <mips/nlm/hal/nae.h> #include <mips/nlm/hal/mdio.h> +#include <mips/nlm/xlp.h> + /* Internal MDIO READ/WRITE Routines */ int nlm_int_gmac_mdio_read(uint64_t nae_base, int bus, int block, @@ -176,12 +178,7 @@ nlm_gmac_mdio_read(uint64_t nae_base, in int intf_type, int phyaddr, int regidx) { uint32_t mdio_ld_cmd; - uint32_t val; - - val = EXT_G_MDIO_CMD_SP | - (phyaddr << EXT_G_MDIO_PHYADDR_POS) | - (regidx << EXT_G_MDIO_REGADDR_POS) | - EXT_G_MDIO_DIV; + uint32_t ctrlval; mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4))); @@ -195,14 +192,22 @@ nlm_gmac_mdio_read(uint64_t nae_base, in EXT_G_MDIO_STAT_MBSY); } - nlm_write_nae_reg(nae_base, + ctrlval = EXT_G_MDIO_CMD_SP | + (phyaddr << EXT_G_MDIO_PHYADDR_POS) | + (regidx << EXT_G_MDIO_REGADDR_POS); + if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax()) + ctrlval |= EXT_G_MDIO_DIV; + else + ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64; + + nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), - val); + ctrlval); nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), - val | (1<<18)); - + ctrlval | (1<<18)); + DELAY(1000); /* poll master busy bit until it is not busy */ while(nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4))) & @@ -210,7 +215,7 @@ nlm_gmac_mdio_read(uint64_t nae_base, in nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), - val); + ctrlval); /* Read the data back */ return nlm_read_nae_reg(nae_base, @@ -236,11 +241,6 @@ nlm_gmac_mdio_write(uint64_t nae_base, i uint32_t mdio_ld_cmd; uint32_t ctrlval; - ctrlval = EXT_G_MDIO_CMD_SP | - (phyaddr << EXT_G_MDIO_PHYADDR_POS) | - (regidx << EXT_G_MDIO_REGADDR_POS) | - EXT_G_MDIO_DIV; - mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4))); if (mdio_ld_cmd & EXT_G_MDIO_CMD_LCD) { @@ -258,6 +258,14 @@ nlm_gmac_mdio_write(uint64_t nae_base, i NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL_DATA+bus*4)), val); + ctrlval = EXT_G_MDIO_CMD_SP | + (phyaddr << EXT_G_MDIO_PHYADDR_POS) | + (regidx << EXT_G_MDIO_REGADDR_POS); + if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax()) + ctrlval |= EXT_G_MDIO_DIV; + else + ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64; + nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), ctrlval); @@ -265,6 +273,7 @@ nlm_gmac_mdio_write(uint64_t nae_base, i nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), ctrlval | EXT_G_MDIO_CMD_LCD); + DELAY(1000); /* poll master busy bit until it is not busy */ while(nlm_read_nae_reg(nae_base, @@ -291,11 +300,17 @@ int nlm_gmac_mdio_reset(uint64_t nae_base, int bus, int block, int intf_type) { + uint32_t ctrlval; + + if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax()) + ctrlval = EXT_G_MDIO_DIV; + else + ctrlval = EXT_G_MDIO_DIV_WITH_HW_DIV64; + nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), - EXT_G_MDIO_MMRST | EXT_G_MDIO_DIV); + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)), + EXT_G_MDIO_MMRST | ctrlval); nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), - EXT_G_MDIO_DIV); + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)), ctrlval); return (0); } Modified: head/sys/mips/nlm/hal/mdio.h ============================================================================== --- head/sys/mips/nlm/hal/mdio.h Mon Jul 9 10:36:43 2012 (r238292) +++ head/sys/mips/nlm/hal/mdio.h Mon Jul 9 10:39:57 2012 (r238293) @@ -81,6 +81,7 @@ #define EXT_G_MDIO_CMD_SC 0x00080000 #define EXT_G_MDIO_MMRST 0x00100000 #define EXT_G_MDIO_DIV 0x0000001E +#define EXT_G_MDIO_DIV_WITH_HW_DIV64 0x00000010 #define EXT_G_MDIO_RD_STAT_MASK 0x0000FFFF #define EXT_G_MDIO_STAT_LFV 0x00010000
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