Date: Sat, 29 Dec 2001 01:27:01 -0500 (EST) From: Stephen Degler <sdegler@degler.net> To: FreeBSD-gnats-submit@freebsd.org Cc: sdegler@degler.net Subject: kern/33294: patches to add support for ethernet on sis 635/735 chipsets Message-ID: <200112290627.fBT6R1h98849@degler.net>
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>Number: 33294
>Category: kern
>Synopsis: patches to add support for ethernet on sis 635/735 chipsets
>Confidential: no
>Severity: non-critical
>Priority: medium
>Responsible: freebsd-bugs
>State: open
>Quarter:
>Keywords:
>Date-Required:
>Class: update
>Submitter-Id: current-users
>Arrival-Date: Fri Dec 28 22:30:00 PST 2001
>Closed-Date:
>Last-Modified:
>Originator: Stephen Degler
>Release: FreeBSD 5.0-CURRENT i386
>Organization:
Very little, at best.
>Environment:
System: FreeBSD crusoe.degler.net 5.0-CURRENT FreeBSD 5.0-CURRENT #0: Fri Dec 7 01:42:27 EST 2001 root@crusoe.degler.net:/usr/src/sys/i386/compile/CRUSOE i386
>Description:
-current (and stable?) do not support embedded ethernet on sis
635 and 735 chipsets. I'm judging this based on an ECS K7S5A
motherboard. The following patches fix the problems with failure to
detect the mii interface, and failure to read the mac address.
The ECS K7S5A uses a Realtek 8201 phy, but I have not added
explicit support for it. The ukphy functionality seems to work
fine.
These changes were derived from the Linux SiS driver, which is
the only source of documentation available for the newer chipsets.
Note that the current sis ethernet driver has a bad hack
to read the mac address for 630 series chipsets. Looking at
the NetBSD sources, it should be possible to replace that with
the newer method, but I don't have the hardware to test with.
>How-To-Repeat:
Fire up -current on a SIS 635/735 based system. See the onboard
ethernet lose.
>Fix:
These patches are working for me:
==========================================================================
--- if_sis.c.orig Sat Dec 29 00:17:49 2001
+++ if_sis.c Sat Dec 29 00:18:13 2001
@@ -147,6 +147,7 @@
static void sis_read_cmos __P((struct sis_softc *, device_t, caddr_t,
int, int));
static device_t sis_find_bridge __P((device_t));
+static void sis_635_reload_mac __P((struct sis_softc *, caddr_t));
#endif
static int sis_miibus_readreg __P((device_t, int, int));
@@ -486,6 +487,33 @@
pci_write_config(bridge, 0x48, reg & ~0x40, 1);
return;
}
+
+/* force 635/735/745 mac to be reloaded from cmos */
+/* may be possible for 630 types as well avoiding ick above */
+/* not yet tested for that case */
+static void sis_635_reload_mac(sc, dest)
+ struct sis_softc *sc;
+ caddr_t dest;
+{
+ u_int32_t i,rxfctl_save;
+
+ rxfctl_save = CSR_READ_4(sc,SIS_RXFILT_CTL);
+ SIS_SETBIT(sc,SIS_CSR,SIS_CSR_RELOAD);
+ CSR_WRITE_4(sc,SIS_CSR,0);
+ /* disable packet filter */
+ CSR_WRITE_4(sc,SIS_RXFILT_CTL,rxfctl_save & ~SIS_RXFILTCTL_ENABLE);
+
+ /* load MAC addr to filter data register */
+ for (i = 0 ; i < 3 ; i++) {
+ CSR_WRITE_4(sc,SIS_RXFILT_CTL,(i << 16));
+ ((u_int16_t *)dest)[i] =
+ (u_int16_t)(CSR_READ_4(sc,SIS_RXFILT_DATA) & 0xffff);
+ }
+ /* enable packet filitering */
+ CSR_WRITE_4(sc,SIS_RXFILT_CTL,rxfctl_save);
+ return;
+}
+
#endif
static int sis_miibus_readreg(dev, phy, reg)
@@ -516,7 +544,8 @@
return(val);
}
- if (sc->sis_type == SIS_TYPE_900 && phy != 0)
+ if (sc->sis_type == SIS_TYPE_900 && sc->sis_rev < SIS_REV_635 &&
+ phy != 0)
return(0);
CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
@@ -556,7 +585,8 @@
return(0);
}
- if (sc->sis_type == SIS_TYPE_900 && phy != 0)
+ if (sc->sis_type == SIS_TYPE_900 && sc->sis_rev < SIS_REV_635 &&
+ phy != 0)
return(0);
CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
@@ -785,6 +815,8 @@
if (pci_get_vendor(dev) == NS_VENDORID)
sc->sis_type = SIS_TYPE_83815;
+ sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
+
/*
* Handle power management nonsense.
*/
@@ -925,13 +957,15 @@
* requires some datasheets that I don't have access
* to at the moment.
*/
- command = pci_read_config(dev, PCIR_REVID, 1);
- if (command == SIS_REV_630S ||
- command == SIS_REV_630E ||
- command == SIS_REV_630EA1)
+
+ if (sc->sis_rev == SIS_REV_630S ||
+ sc->sis_rev == SIS_REV_630E ||
+ sc->sis_rev == SIS_REV_630EA1)
sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
+ else if ( sc->sis_rev == SIS_REV_635 )
+ sis_635_reload_mac(sc, (caddr_t)&eaddr);
else
-#endif
+#endif /* __i386__ */
sis_read_eeprom(sc, (caddr_t)&eaddr,
SIS_EE_NODEADDR, 3, 0);
break;
==========================================================================
--- if_sisreg.h.orig Sat Dec 29 00:18:00 2001
+++ if_sisreg.h Sat Dec 29 00:18:19 2001
@@ -105,6 +105,7 @@
#define SIS_CSR_RX_RESET 0x00000020
#define SIS_CSR_SOFTINTR 0x00000080
#define SIS_CSR_RESET 0x00000100
+#define SIS_CSR_RELOAD 0x00000400
#define SIS_CFG_BIGENDIAN 0x00000001
#define SIS_CFG_PERR_DETECT 0x00000008
@@ -381,7 +382,7 @@
#define SIS_REV_630E 0x0081
#define SIS_REV_630S 0x0082
#define SIS_REV_630EA1 0x0083
-
+#define SIS_REV_635 0x0090
/*
* NatSemi vendor ID
*/
@@ -412,6 +413,7 @@
device_t sis_miibus;
u_int8_t sis_unit;
u_int8_t sis_type;
+ u_int8_t sis_rev;
u_int8_t sis_link;
struct sis_list_data sis_ldata;
bus_dma_tag_t sis_parent_tag;
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