Date: Thu, 17 Apr 2008 17:33:59 -0700 From: "David O'Brien" <obrien@freebsd.org> To: gnn@freebsd.org Cc: freebsd-current@freebsd.org, Andrew Gallatin <gallatin@cs.duke.edu> Subject: Re: TSC Timecounter and multi-core/SMP Message-ID: <20080418003359.GC11705@dragon.NUXI.org> In-Reply-To: <m27iezwonx.wl%gnn@neville-neil.com> References: <m2d4oy8n30.wl%gnn@neville-neil.com> <18431.23276.913397.188219@grasshopper.cs.duke.edu> <m27iezwonx.wl%gnn@neville-neil.com>
next in thread | previous in thread | raw e-mail | index | archive | help
On Tue, Apr 15, 2008 at 04:41:22PM +0900, gnn@freebsd.org wrote: > I also believe that at least per processor there is only 1 TSC, that > is, on a 2 or 4 core, all cores share the same TSC. Nope. (at least nope for AMD processors) -- -- David (obrien@FreeBSD.org)
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?20080418003359.GC11705>