Date: Fri, 20 Jun 2003 00:02:38 -0700 From: Terry Lambert <tlambert2@mindspring.com> To: Marcel Moolenaar <marcel@xcllnt.net> Cc: Julian Elischer <julian@elischer.org> Subject: Re: Implementing TLS: step 1 Message-ID: <3EF2B18E.FB346477@mindspring.com> References: <20030620031326.GA2260@dhcp01.pn.xcllnt.net> <20030620034647.GB2260@dhcp01.pn.xcllnt.net>
next in thread | previous in thread | raw e-mail | index | archive | help
Marcel Moolenaar wrote: > On Thu, Jun 19, 2003 at 11:39:42PM -0400, Daniel Eischen wrote: > > > Q2: Given that libthr has been ported to ia64, what needs to be done > > > to port libkse to ia64 (roughtly)? > > > > libpthread/arch/i386/include/ksd.h: > > libpthread/arch/i386/include/atomic_ops.h > > libpthread/arch/i386/include/pthread_md.h > > libpthread/arch/i386/i386: > > No kernel code? Hmmm, looks like something that's worth giving a > shot. If we have libkse on ia64, we can more easily work on the > issues related to TLS... You guys are missing something. Daniel's earlier point about the IA64 documentation not specifying that the TP point to TLS, rather than a data structure that contains a pointer to TLS is correct (from my reading of both references posted by Marcel). On the other hand, zeroing the TP register in user space to indicate that upcalls are disabled is probably illegal, from the point of vie of that same documentation, so there needs to be another way to do the deed. The problem I forsee here is that it's possible that the SMT cores assign special significance to this register when doing instruction reordering inside the pipeline, and this would definitely break any benefits you would otherwise have obtained from using the register for real threads, if that's the case. Note that this predominantly applies only on UP machines; any MP machines will have a statistical chance of 1 in <num CPU> of breaking the pipelining anyway (IMO, Intel is amining SMT machines at the UP market, more than the SMP market, and SMP users should not expect much benefit: negaffinity will win you more cycles than 1/2-a-CPU-core-when-the-other-1/2-is-idle). -- Terry
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?3EF2B18E.FB346477>