Skip site navigation (1)Skip section navigation (2)
Date:      Mon, 17 Apr 2023 13:50:00 GMT
From:      Mark Johnston <markj@FreeBSD.org>
To:        src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org
Subject:   git: d95fbf4e1a12 - main - riscv: save the thread pointer in both modes
Message-ID:  <202304171350.33HDo0A8072708@gitrepo.freebsd.org>

next in thread | raw e-mail | index | archive | help
The branch main has been updated by markj:

URL: https://cgit.FreeBSD.org/src/commit/?id=d95fbf4e1a12565908b04b442263fe60c9e890b4

commit d95fbf4e1a12565908b04b442263fe60c9e890b4
Author:     Mark Johnston <markj@FreeBSD.org>
AuthorDate: 2023-04-17 13:44:44 +0000
Commit:     Mark Johnston <markj@FreeBSD.org>
CommitDate: 2023-04-17 13:49:52 +0000

    riscv: save the thread pointer in both modes
    
    The contents of frame->tf_tp are uninitialized if accessed by DTrace (in
    probe context), resulting in a panic when trying to access the memory
    pointed to by tp. This saves the thread pointer to the trap frame when
    handling both userland and kernel exceptions.
    
    Reviewed by:    markj, mhorne
    MFC after:      2 weeks
    Sponsored by:   The FreeBSD Foundation
    Differential Revision:  https://reviews.freebsd.org/D39582
---
 sys/riscv/riscv/exception.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sys/riscv/riscv/exception.S b/sys/riscv/riscv/exception.S
index cf06c364de46..a68e7938e537 100644
--- a/sys/riscv/riscv/exception.S
+++ b/sys/riscv/riscv/exception.S
@@ -56,6 +56,8 @@ __FBSDID("$FreeBSD$");
 	/* Load our pcpu */
 	sd	tp, (TF_TP)(sp)
 	ld	tp, (TF_SIZE)(sp)
+.else
+	sd	tp, (TF_TP)(sp)
 .endif
 
 	sd	t0, (TF_T + 0 * 8)(sp)



Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?202304171350.33HDo0A8072708>