Date: Tue, 15 May 2001 12:41:13 -0700 (PDT) From: "Justin T. Gibbs" <gibbs@FreeBSD.org> To: cvs-committers@FreeBSD.org, cvs-all@FreeBSD.org Subject: cvs commit: src/sys/dev/aic7xxx ahc_eisa.c ahc_pci.c aic7770.c aic7xxx.c aic7xxx.h aic7xxx.reg aic7xxx.seq aic7xxx_93cx6.c aic7xxx_freebsd.c aic7xxx_freebsd.h aic7xxx_inline.h aic7xxx_pci.c Message-ID: <200105151941.f4FJfDO30362@freefall.freebsd.org>
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gibbs 2001/05/15 12:41:13 PDT
Modified files:
sys/dev/aic7xxx ahc_eisa.c ahc_pci.c aic7770.c aic7xxx.c
aic7xxx.h aic7xxx.reg aic7xxx.seq
aic7xxx_93cx6.c aic7xxx_freebsd.c
aic7xxx_freebsd.h aic7xxx_inline.h
aic7xxx_pci.c
Log:
ahc_eisa.c:
ahc_pci.c:
Prepare for making ahc a module by adding module dependency
and version info.
aic7770.c:
Remove linux header ifdefs. The headers are handled differently
in Linux where local includes (those using "'s instead of <>'s)
are allowed.
Don't map our interrupt until after we are fully setup to
handle interrupts. Our interrupt line may be shared so
an interrupt could occur at any time.
aic7xxx.c:
Remove linux header ifdefs.
current->curr to avoid Linux's use of current as a
#define for the current task on some architectures.
Add a helper function, ahc_assert_atn(), for use in
message phases we handle manually. This hides the fact
that U160 chips with the expected phase matching disabled
need to have SCSISIGO updated differently.
if (ahc_check_residual(scb) != 0)
ahc_calc_residual(scb);
else
ahc_set_residual(scb, 0);
becomes:
ahc_update_residual(scb);
Modify scsi parity error (or CRC error) handling to
reflect expected phase being disabled on U160 chips.
Move SELTO handling above BUSFREE handling so we can
use the new busfree interrupt behavior on U160 chips.
In ahc_build_transfer_msg() filter the period and ppr_options
prior to deciding whether a PPR message is required.
ppr_options may be forced to zero which will effect our
decision.
Correct a long standing but latent bug in ahc_find_syncrate().
We could choose a DT only rate even though DT transfers were
disabled. In the CAM environment this was unlikely as CAM
filters our rate to a non-DT value if the device does not
support such rates.
When displaing controller characteristics, include the
speed of the chip. This way we can modify the transfer
speed based on optional features that are enabled/disabled
in a particular application.
Add support for switching from fully blown tagged queing
to just using simple queue tags should the device reject
an ordered tag.
Remove per-target "current" disconnect and tag queuing
enable flags. These should be per-device and are not
referenced internally be the driver, so we let the OSM
track this state if it needs to.
Use SCSI-3 message terminology.
aic7xxx.h:
The real 7850 does not support Ultra modes, but there are
several cards that use the generic 7850 PCI ID even though
they are using an Ultra capable chip (7859/7860). We start
out with the AHC_ULTRA feature set and then check the
DEVSTATUS register to determine if the capability is really
present.
current -> curr
ahc_calc_residual() is no longer static allowing it to
be called from ahc_update_residual() in aic7xxx_inline.h.
Update some serial eeprom definitions for the latest
BIOS versions.
aic7xxx.reg:
Add a combined DATA_PHASE mask to the SCSIPHASE register
definition to simplify some sequencer code.
aic7xxx.seq:
Take advantage of some performance features available only
on the U160 chips. The auto-ack feature allows us to ack
data-in phases up to the data-fifo size while the sequencer
is still setting up the DMA engine. This greatly reduces
read transfer latency and simplifies testing for transfer
complete (check SCSIEN only). We also disable the expected
phase feature, and enable the new bus free interrupt behavior,
to avoid a few instructions.
Re-arrange the Ultra2+ data phase handling to allow us to
do more work in parallel with the data fifo flushing on a
read.
On an SDTR, ack the message immediately so the target can
prepare the next phase or message byte in parallel with
our work to honor the message.
aic7xxx_93cx6.c:
Remove linux header ifdefs.
aic7xxx_freebsd.c:
current -> curr
Add a module event handler.
Handle tag downgrades in our ahc_send_async() handler.
We won't be able to downgrade to "basic queuing" until
CAM is made aware of this queuing type.
aic7xxx_freebsd.h:
Include cleanups.
Define offsetof if required.
Correct a few comments.
Update prototype of ahc_send_async().
aic7xxx_inline.h:
Implement ahc_update_residual().
aic7xxx_pci.c:
Remove linux header ifdefs.
Correct a few product strings.
Enable several U160 performance enhancing features.
Modify Ultra capability determination so we will enable
Ultra speeds on devices with a 7850 PCI id that happen
to really be a 7859 or 7860.
Don't map our interrupt until after we are fully setup to
handle interrupts. Our interrupt line may be shared so
an interrupt could occur at any time.
Revision Changes Path
1.22 +3 -1 src/sys/dev/aic7xxx/ahc_eisa.c
1.42 +3 -1 src/sys/dev/aic7xxx/ahc_pci.c
1.6 +6 -14 src/sys/dev/aic7xxx/aic7770.c
1.75 +166 -156 src/sys/dev/aic7xxx/aic7xxx.c
1.39 +31 -16 src/sys/dev/aic7xxx/aic7xxx.h
1.38 +3 -2 src/sys/dev/aic7xxx/aic7xxx.reg
1.117 +153 -67 src/sys/dev/aic7xxx/aic7xxx.seq
1.14 +1 -9 src/sys/dev/aic7xxx/aic7xxx_93cx6.c
1.25 +48 -8 src/sys/dev/aic7xxx/aic7xxx_freebsd.c
1.10 +11 -6 src/sys/dev/aic7xxx/aic7xxx_freebsd.h
1.16 +11 -10 src/sys/dev/aic7xxx/aic7xxx_inline.h
1.15 +25 -33 src/sys/dev/aic7xxx/aic7xxx_pci.c
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