Date: Mon, 4 Jul 2011 19:51:26 +0000 (UTC) From: Marcel Moolenaar <marcel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r223767 - in projects/llvm-ia64: contrib/llvm/lib/Target/IA64 lib/clang/include Message-ID: <201107041951.p64JpQDk032074@svn.freebsd.org>
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Author: marcel Date: Mon Jul 4 19:51:26 2011 New Revision: 223767 URL: http://svn.freebsd.org/changeset/base/223767 Log: o Implement LowerFormalArguments() LowerReturn() using CallingConv and for general registers only. o Implement IA64InstrInfo::copyPhysReg() for general registers. This is needed during lowering and before copy elimination. o Move IA instruction definitions from IA64.td to IA64InstrFormat.td and IA64InstrInfo.td. Add the register form of the add instruction and add the branch return instruction. o Rename register classes to something a lot shorter: BR instead of Branch, etc. o Define branch registers properly. THis includes their DWARF register numbers. Flesh out the general registers in a similar manner. o Add the target-specific RET_FLAG SDNode type, that's used to represent function returns. o Implement IA64MCInstLower::Lower() for general registers, so that we can lower add instructions to machine code. Given that the assemblerwriter is based on machine code, this means that we can properly compile: long add(long x, long y) { return (x + y); } into: .file "add.c" .text .global add .align 32 .type add,@function add: add r8=r33,r32 br.ret.sptk rp .tmp0: .size add, .tmp0-add Added: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrFormats.td projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrInfo.td projects/llvm-ia64/lib/clang/include/IA64GenCallingConv.inc Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64.td projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrInfo.cpp projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrInfo.h projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64MCInstLower.cpp projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64RegisterInfo.td projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.cpp projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.h Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64.td ============================================================================== --- projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64.td Mon Jul 4 19:33:04 2011 (r223766) +++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64.td Mon Jul 4 19:51:26 2011 (r223767) @@ -1,6 +1,5 @@ include "llvm/Target/Target.td" -include "IA64RegisterInfo.td" // // Subtargets @@ -24,20 +23,19 @@ def : IA64Impl<"montecito", [FeatureLong def : IA64Impl<"montvale", [FeatureLongBranch]>; // -// Calling Convention +// Registers // -include "IA64CallingConv.td" +include "IA64RegisterInfo.td" // // Instructions // -class IA64Instruction<dag outs, dag ins> : Instruction { - let Namespace = "IA64"; - let OutOperandList = outs; - let InOperandList = ins; -} +include "IA64InstrInfo.td" -def NOP : IA64Instruction<(outs), (ins)>; +// +// Calling Convention +// +include "IA64CallingConv.td" def IA64InstrInfo : InstrInfo; Added: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrFormats.td ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrFormats.td Mon Jul 4 19:51:26 2011 (r223767) @@ -0,0 +1,65 @@ + +class +IA64Instruction<bits<4> op, dag outs, dag ins, string as, list<dag> pat> : + Instruction +{ + let Namespace = "IA64"; + // let Inst{40-37} = op; + let OutOperandList = outs; + let InOperandList = ins; + let AsmString = as; + let Pattern= pat; +} + +// +// A1-A10 +// + +class +A1<bits<9> x, dag outs, dag ins, string as, list<dag> pat> : + IA64Instruction<8, outs, ins, as, pat> +{ + // let Inst{35-27} = x; +} + +// +// B1-B9 +// + +class bwh<bits<2> h> +{ + bits<2> wh = h; +} +def sptk : bwh<0>; +def spnt : bwh<1>; +def dptk : bwh<2>; +def dpnt : bwh<3>; + +class +B4<bits<6> x6, bits<3> btype, bwh wh, dag outs, dag ins, string as, + list<dag> pat> : + IA64Instruction<0, outs, ins, as, pat> +{ + // let Inst{35} = 0; // Branch Cache Deallocation Hint (0=none; 1=clr) + // let Inst{34-33} = wh; + // let Inst{32-27} = x6; + // let Inst{12} = 0; // Sequential Prefetch Hint (0=few; 1=many) + // let Inst{8-6} = btype; +} + +// +// F1-F16 +// + +// +// I1-I30 +// + +// +// M1-M48 +// + +// +// X1-X5 +// + Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrInfo.cpp ============================================================================== --- projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrInfo.cpp Mon Jul 4 19:33:04 2011 (r223766) +++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrInfo.cpp Mon Jul 4 19:51:26 2011 (r223767) @@ -20,3 +20,21 @@ IA64InstrInfo::IA64InstrInfo(IA64TargetM { // nothing to do } + +void +IA64InstrInfo::copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, + unsigned SrcReg, bool KillSrc) const +{ + bool GRDest = IA64::GRRegClass.contains(DestReg); + bool GRSrc = IA64::GRRegClass.contains(SrcReg); + + if (GRDest && GRSrc) { + MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(IA64::ADD), DestReg); + MIB.addReg(IA64::R0); + MIB.addReg(SrcReg, getKillRegState(KillSrc)); + return; + } + + llvm_unreachable(__func__); +} Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrInfo.h ============================================================================== --- projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrInfo.h Mon Jul 4 19:33:04 2011 (r223766) +++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrInfo.h Mon Jul 4 19:51:26 2011 (r223767) @@ -22,6 +22,9 @@ namespace llvm { /// virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } + virtual void copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, + unsigned SrcReg, bool KillSrc) const; }; } // namespace llvm Added: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrInfo.td ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64InstrInfo.td Mon Jul 4 19:51:26 2011 (r223767) @@ -0,0 +1,20 @@ + +include "IA64InstrFormats.td" + +def retflag : SDNode<"IA64ISD::RET_FLAG", SDTNone, + [SDNPHasChain, SDNPOptInGlue]>; + +def ADD : A1<0, (outs GR:$r1), (ins GR:$r2, GR:$r3), + "add\t$r1=$r2,$r3", + [(set GR:$r1, (add GR:$r2, GR:$r3))]>; + +def BR_RET : B4<21, 4, sptk, (outs), (ins), + "br.ret.sptk\trp", [(retflag)]> +{ + let isReturn = 1; + let isTerminator = 1; + let isBarrier = 1; +} + +def NOP : IA64Instruction<0, (outs), (ins), "nop", []>; + Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64MCInstLower.cpp ============================================================================== --- projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64MCInstLower.cpp Mon Jul 4 19:33:04 2011 (r223766) +++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64MCInstLower.cpp Mon Jul 4 19:51:26 2011 (r223767) @@ -54,5 +54,24 @@ IA64MCInstLower::LowerSymbolOperand(cons void IA64MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { - llvm_unreachable(__func__); + + OutMI.setOpcode(MI->getOpcode()); + + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + + MCOperand MCOp; + switch (MO.getType()) { + case MachineOperand::MO_Register: + if (MO.isImplicit()) + continue; + MCOp = MCOperand::CreateReg(MO.getReg()); + break; + default: + MI->dump(); + llvm_unreachable(__func__); + } + + OutMI.addOperand(MCOp); + } } Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64RegisterInfo.td ============================================================================== --- projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64RegisterInfo.td Mon Jul 4 19:33:04 2011 (r223766) +++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64RegisterInfo.td Mon Jul 4 19:51:26 2011 (r223767) @@ -26,7 +26,7 @@ def B5 : IA64Register<"b5">, DwarfRegNum def B6 : IA64Register<"b6">, DwarfRegNum<[326]>; def B7 : IA64Register<"b7">, DwarfRegNum<[327]>; -def Branch : IA64RegisterClass<[i64], 64, +def BR : IA64RegisterClass<[i64], 64, [B6, B7, B0, B1, B2, B3, B4, B5]>; // @@ -67,34 +67,62 @@ def F29 : IA64Register<"f29">; def F30 : IA64Register<"f30">; def F31 : IA64Register<"f31">; -def FloatingPoint : IA64RegisterClass<[f128], 128, +def FR : IA64RegisterClass<[f128], 128, [F0, F1, F2, F3, F4, F5, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; // // General registers // -def R0 : IA64Register<"r0">; -def R1 : IA64Register<"r1">; -def R4 : IA64Register<"r4">; -def R5 : IA64Register<"r5">; -def R6 : IA64Register<"r6">; -def R7 : IA64Register<"r7">; -def R8 : IA64Register<"r8">; -def R12 : IA64Register<"r12">; -def R13 : IA64Register<"r13">; -// XXX -def R32 : IA64Register<"r32">; -def R33 : IA64Register<"r33">; -def R34 : IA64Register<"r34">; -def R35 : IA64Register<"r35">; -def R36 : IA64Register<"r36">; -def R37 : IA64Register<"r37">; -def R38 : IA64Register<"r38">; -def R39 : IA64Register<"r39">; - -def General : IA64RegisterClass<[i64], 64, - [R0, R1, R4, R5, R6, R7, R8, R12, R13]>; +def R0 : IA64Register<"r0">, DwarfRegNum<[0]>; +def R1 : IA64Register<"r1">, DwarfRegNum<[1]>; +def R2 : IA64Register<"r2">, DwarfRegNum<[2]>; +def R3 : IA64Register<"r3">, DwarfRegNum<[3]>; +def R4 : IA64Register<"r4">, DwarfRegNum<[4]>; +def R5 : IA64Register<"r5">, DwarfRegNum<[5]>; +def R6 : IA64Register<"r6">, DwarfRegNum<[6]>; +def R7 : IA64Register<"r7">, DwarfRegNum<[7]>; +def R8 : IA64Register<"r8">, DwarfRegNum<[8]>; +def R9 : IA64Register<"r9">, DwarfRegNum<[9]>; +def R10 : IA64Register<"r10">, DwarfRegNum<[10]>; +def R11 : IA64Register<"r11">, DwarfRegNum<[11]>; +def R12 : IA64Register<"r12">, DwarfRegNum<[12]>; +def R13 : IA64Register<"r13">, DwarfRegNum<[13]>; +def R14 : IA64Register<"r14">, DwarfRegNum<[14]>; +def R15 : IA64Register<"r15">, DwarfRegNum<[15]>; +def R16 : IA64Register<"r16">, DwarfRegNum<[16]>; +def R17 : IA64Register<"r17">, DwarfRegNum<[17]>; +def R18 : IA64Register<"r18">, DwarfRegNum<[18]>; +def R19 : IA64Register<"r19">, DwarfRegNum<[19]>; +def R20 : IA64Register<"r20">, DwarfRegNum<[20]>; +def R21 : IA64Register<"r21">, DwarfRegNum<[21]>; +def R22 : IA64Register<"r22">, DwarfRegNum<[22]>; +def R23 : IA64Register<"r23">, DwarfRegNum<[23]>; +def R24 : IA64Register<"r24">, DwarfRegNum<[24]>; +def R25 : IA64Register<"r25">, DwarfRegNum<[25]>; +def R26 : IA64Register<"r26">, DwarfRegNum<[26]>; +def R27 : IA64Register<"r27">, DwarfRegNum<[27]>; +def R28 : IA64Register<"r28">, DwarfRegNum<[28]>; +def R29 : IA64Register<"r29">, DwarfRegNum<[29]>; +def R30 : IA64Register<"r30">, DwarfRegNum<[30]>; +def R31 : IA64Register<"r31">, DwarfRegNum<[31]>; +def R32 : IA64Register<"r32">, DwarfRegNum<[32]>; +def R33 : IA64Register<"r33">, DwarfRegNum<[33]>; +def R34 : IA64Register<"r34">, DwarfRegNum<[34]>; +def R35 : IA64Register<"r35">, DwarfRegNum<[35]>; +def R36 : IA64Register<"r36">, DwarfRegNum<[36]>; +def R37 : IA64Register<"r37">, DwarfRegNum<[37]>; +def R38 : IA64Register<"r38">, DwarfRegNum<[38]>; +def R39 : IA64Register<"r39">, DwarfRegNum<[39]>; + +def GR : IA64RegisterClass<[i64], 64, + [R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, + R28, R29, R30, R31, + R8, R9, R10, R11, + R2, R3, + R32, R33, R34, R35, R36, R37, R38, R39, + R4, R5, R6, R7, + R1, R12, R13, R0]>; // // Pregicate registers @@ -154,7 +182,7 @@ def P61 : IA64Register<"p61">; def P62 : IA64Register<"p62">; def P63 : IA64Register<"p63">; -def Predicate : IA64RegisterClass<[i1], 0, +def P : IA64RegisterClass<[i1], 0, [P0, P1, P2, P3, P4, P5, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, P36, P37, P38, P39, P40, P41, P42, P43, P44, P45, P46, P47, P48, P49, P50, P51, P52, P53, P54, P55, Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.cpp ============================================================================== --- projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.cpp Mon Jul 4 19:33:04 2011 (r223766) +++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.cpp Mon Jul 4 19:51:26 2011 (r223767) @@ -28,6 +28,8 @@ using namespace llvm; +#include "IA64GenCallingConv.inc" + IA64TargetLowering::IA64TargetLowering(IA64TargetMachine &tm) : TargetLowering(tm, new TargetLoweringObjectFileELF()), Subtarget(*tm.getSubtargetImpl()), @@ -36,10 +38,10 @@ IA64TargetLowering::IA64TargetLowering(I TD = getTargetData(); // Set up the register classes. - addRegisterClass(MVT::i64, &IA64::BranchRegClass); - addRegisterClass(MVT::f128, &IA64::FloatingPointRegClass); - addRegisterClass(MVT::i64, &IA64::GeneralRegClass); - addRegisterClass(MVT::i1, &IA64::PredicateRegClass); + addRegisterClass(MVT::i64, &IA64::BRRegClass); + addRegisterClass(MVT::f128, &IA64::FRRegClass); + addRegisterClass(MVT::i64, &IA64::GRRegClass); + addRegisterClass(MVT::i1, &IA64::PRegClass); // Compute derived properties from the register classes computeRegisterProperties(); @@ -51,6 +53,18 @@ IA64TargetLowering::IA64TargetLowering(I setJumpBufAlignment(16); } +const char * +IA64TargetLowering::getTargetNodeName(unsigned Opcode) const +{ + const char *nn; + + switch (Opcode) { + case IA64ISD::RET_FLAG: nn = "IA64ISD::RET_FLAG"; break; + default: nn = NULL; break; + } + return nn; +} + SDValue IA64TargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, @@ -72,21 +86,37 @@ IA64TargetLowering::LowerFormalArguments SmallVectorImpl<SDValue> &InVals) const { MachineFunction &MF = DAG.getMachineFunction(); - SDValue Val; + SmallVector<CCValAssign, 16> ArgLocs; + CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), ArgLocs, + *DAG.getContext()); DEBUG(dbgs() << "XXX: IA64TargetLowering::" << __func__ << "\n"); - for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { - EVT vt = Ins[ArgNo].VT; + CCInfo.AllocateStack(0, 8); + CCInfo.AnalyzeFormalArguments(Ins, CC_IA64); - unsigned VReg = - MF.getRegInfo().createVirtualRegister(&IA64::GeneralRegClass); - MF.getRegInfo().addLiveIn(IA64::R32, VReg); - Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); - InVals.push_back(Val); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + EVT ValVT = VA.getValVT(); + TargetRegisterClass *RC; + + if (!VA.isRegLoc()) + llvm_unreachable(__func__); + + switch (ValVT.getSimpleVT().SimpleTy) { + case MVT::i64: + RC = &IA64::GRRegClass; + break; + default: + llvm_unreachable(__func__); + } + + unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); + SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); + InVals.push_back(ArgValue); - DEBUG(dbgs() << ArgNo << ": " << vt.getSimpleVT().SimpleTy << " -> " << - VReg << "\n:"); + DEBUG(dbgs() << i << ": " << ValVT.getSimpleVT().SimpleTy << " -> " << + Reg << "\n"); } return Chain; @@ -99,8 +129,34 @@ IA64TargetLowering::LowerReturn(SDValue SelectionDAG &DAG) const { MachineFunction &MF = DAG.getMachineFunction(); + SmallVector<CCValAssign, 16> RVLocs; + CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, + *DAG.getContext()); + CCInfo.AnalyzeReturn(Outs, RetCC_IA64); DEBUG(dbgs() << "XXX: IA64TargetLowering::" <<__func__ << "\n"); - return Chain; + if (MF.getRegInfo().liveout_empty()) { + for (unsigned i = 0; i != RVLocs.size(); ++i) + MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); + } + + SDValue Flag; + + for (unsigned i = 0; i != RVLocs.size(); ++i) { + CCValAssign &VA = RVLocs[i]; + + if (!VA.isRegLoc()) + llvm_unreachable(__func__); + + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); + Flag = Chain.getValue(1); + } + + SDValue result; + if (Flag.getNode()) + result = DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, Chain, Flag); + else + result = DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, Chain); + return result; } Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.h ============================================================================== --- projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.h Mon Jul 4 19:33:04 2011 (r223766) +++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.h Mon Jul 4 19:51:26 2011 (r223767) @@ -7,6 +7,15 @@ namespace llvm { + namespace IA64ISD { + + enum { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + RET_FLAG, // Return with a flag operand (in operand 0). + }; + + } // namespace IA64ISD + class IA64Subtarget; class IA64TargetMachine; @@ -18,6 +27,8 @@ namespace llvm { public: explicit IA64TargetLowering(IA64TargetMachine &TM); + virtual const char *getTargetNodeName(unsigned Opcode) const; + virtual SDValue LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, Added: projects/llvm-ia64/lib/clang/include/IA64GenCallingConv.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/llvm-ia64/lib/clang/include/IA64GenCallingConv.inc Mon Jul 4 19:51:26 2011 (r223767) @@ -0,0 +1,2 @@ +/* $FreeBSD$ */ +#include "IA64GenCallingConv.inc.h"
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