Date: Thu, 20 Nov 1997 17:31:16 GMT From: mouth@ibm.net (John Kelly) To: Bruce Evans <bde@zeta.org.au> Cc: hackers@freebsd.org Subject: Re: Status of 650 UART support Message-ID: <34746b1f.1864429@smtp-gw01.ny.us.ibm.net> In-Reply-To: <199711200737.SAA28030@godzilla.zeta.org.au> References: <199711200737.SAA28030@godzilla.zeta.org.au>
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On Thu, 20 Nov 1997 18:37:00 +1100, Bruce Evans <bde@zeta.org.au> wrote: >I think you can actually ready bit 7 to see if there is a full fifo >(with no parity/framing/overrun errors) and, if it is set, read the >entire fifo before reading the LSR again. This gives close to one I/O >per input byte. It is a bit tricky to handle error cases and quitting >properly - we don't want to fall back to two I/O's per input byte. The Startech databook makes no mention of LSR bit 7 indicating a full FIFO, only a dirty one. Same for all the literature I have on the NS 16550. Apparently you can use the FIFO trigger level to read a block of bytes without checking LSR bit 0 every time -- the Startech data book even suggests it. To handle all cases, especially multiport shared interrupt cards where you don't know which UART generated the receiver interrupt, you must first check the IIR (Startech calls it the ISR -- interrupt Status register) to see if the UART generated a received data interrupt. After emptying the block, you could leave any remaining characters in the FIFO, and simply get them on the next interrupt, avoiding the need of checking LSR bit 0 for bytes beyond the block size. John
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