Date: Mon, 30 Nov 2015 10:06:12 -0800 From: Adrian Chadd <adrian.chadd@gmail.com> To: Michal Meloun <mmel@freebsd.org> Cc: "src-committers@freebsd.org" <src-committers@freebsd.org>, "svn-src-all@freebsd.org" <svn-src-all@freebsd.org>, "svn-src-head@freebsd.org" <svn-src-head@freebsd.org> Subject: Re: svn commit: r291492 - in head/sys/arm: arm include Message-ID: <CAJ-VmomxHPat%2BU8uNHs00zF73XdeW2KrvE1m=mVyWQ3dQJqXrw@mail.gmail.com> In-Reply-To: <201511301709.tAUH9P9E089512@repo.freebsd.org> References: <201511301709.tAUH9P9E089512@repo.freebsd.org>
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Hiya! What's the semantics of this? The mips24k/mips74k cores support a kind of write combining but only within a cache line - ie, it buffers writes to the same cache line, then the first non-cacheline access flushes it out. It's for things like accelerated framebuffer writes. Is this similar to what you've just added? -a
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