Date: Wed, 20 Oct 2010 07:22:34 +0000 (UTC) From: Alexander Motin <mav@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r214099 - head/sys/dev/mvs Message-ID: <201010200722.o9K7MYmT041065@svn.freebsd.org>
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Author: mav Date: Wed Oct 20 07:22:34 2010 New Revision: 214099 URL: http://svn.freebsd.org/changeset/base/214099 Log: Some style cleanup: - remove commented debugging code; - wrap long lines. Modified: head/sys/dev/mvs/mvs.c head/sys/dev/mvs/mvs_pci.c head/sys/dev/mvs/mvs_soc.c Modified: head/sys/dev/mvs/mvs.c ============================================================================== --- head/sys/dev/mvs/mvs.c Wed Oct 20 06:38:54 2010 (r214098) +++ head/sys/dev/mvs/mvs.c Wed Oct 20 07:22:34 2010 (r214099) @@ -57,7 +57,8 @@ static int mvs_ch_deinit(device_t dev); static int mvs_ch_suspend(device_t dev); static int mvs_ch_resume(device_t dev); static void mvs_dmainit(device_t dev); -static void mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); +static void mvs_dmasetupc_cb(void *xsc, + bus_dma_segment_t *segs, int nsegs, int error); static void mvs_dmafini(device_t dev); static void mvs_slotsalloc(device_t dev); static void mvs_slotsfree(device_t dev); @@ -79,7 +80,8 @@ static void mvs_crbq_intr(device_t dev); static void mvs_begin_transaction(device_t dev, union ccb *ccb); static void mvs_legacy_execute_transaction(struct mvs_slot *slot); static void mvs_timeout(struct mvs_slot *slot); -static void mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); +static void mvs_dmasetprd(void *arg, + bus_dma_segment_t *segs, int nsegs, int error); static void mvs_requeue_frozen(device_t dev); static void mvs_execute_transaction(struct mvs_slot *slot); static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et); @@ -314,9 +316,11 @@ mvs_dmainit(device_t dev) if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0, &ch->dma.workrq_map)) goto error; - if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map, ch->dma.workrq, - MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) || dcba.error) { - bus_dmamem_free(ch->dma.workrq_tag, ch->dma.workrq, ch->dma.workrq_map); + if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map, + ch->dma.workrq, MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) || + dcba.error) { + bus_dmamem_free(ch->dma.workrq_tag, + ch->dma.workrq, ch->dma.workrq_map); goto error; } ch->dma.workrq_bus = dcba.maddr; @@ -329,9 +333,11 @@ mvs_dmainit(device_t dev) if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0, &ch->dma.workrp_map)) goto error; - if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map, ch->dma.workrp, - MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) || dcba.error) { - bus_dmamem_free(ch->dma.workrp_tag, ch->dma.workrp, ch->dma.workrp_map); + if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map, + ch->dma.workrp, MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) || + dcba.error) { + bus_dmamem_free(ch->dma.workrp_tag, + ch->dma.workrp, ch->dma.workrp_map); goto error; } ch->dma.workrp_bus = dcba.maddr; @@ -371,7 +377,8 @@ mvs_dmafini(device_t dev) } if (ch->dma.workrp_bus) { bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map); - bus_dmamem_free(ch->dma.workrp_tag, ch->dma.workrp, ch->dma.workrp_map); + bus_dmamem_free(ch->dma.workrp_tag, + ch->dma.workrp, ch->dma.workrp_map); ch->dma.workrp_bus = 0; ch->dma.workrp_map = NULL; ch->dma.workrp = NULL; @@ -382,7 +389,8 @@ mvs_dmafini(device_t dev) } if (ch->dma.workrq_bus) { bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map); - bus_dmamem_free(ch->dma.workrq_tag, ch->dma.workrq, ch->dma.workrq_map); + bus_dmamem_free(ch->dma.workrq_tag, + ch->dma.workrq, ch->dma.workrq_map); ch->dma.workrq_bus = 0; ch->dma.workrq_map = NULL; ch->dma.workrq = NULL; @@ -444,14 +452,16 @@ mvs_setup_edma_queues(device_t dev) ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32); ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff); ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff); - bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, + BUS_DMASYNC_PREWRITE); /* Reponses queue. */ bzero(ch->dma.workrp, 256); work = ch->dma.workrp_bus; ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32); ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff); ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff); - bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, BUS_DMASYNC_PREREAD); + bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, + BUS_DMASYNC_PREREAD); ch->out_idx = 0; ch->in_idx = 0; } @@ -678,20 +688,15 @@ mvs_ch_intr(void *data) int i, ccs, port = -1, selfdis = 0; int edma = (ch->numtslots != 0 || ch->numdslots != 0); -//device_printf(dev, "irq cause %02x EDMA %d IEC %08x\n", -// arg->cause, edma, ATA_INL(ch->r_mem, EDMA_IEC)); /* New item in response queue. */ if ((arg->cause & 2) && edma) mvs_crbq_intr(dev); /* Some error or special event. */ if (arg->cause & 1) { iec = ATA_INL(ch->r_mem, EDMA_IEC); -//device_printf(dev, "irq cause %02x EDMA %d IEC %08x\n", -// arg->cause, edma, iec); if (iec & EDMA_IE_SERRINT) { serr = ATA_INL(ch->r_mem, SATA_SE); ATA_OUTL(ch->r_mem, SATA_SE, serr); -//device_printf(dev, "SERR %08x\n", serr); } /* EDMA self-disabled due to error. */ if (iec & EDMA_IE_ESELFDIS) @@ -706,7 +711,6 @@ mvs_ch_intr(void *data) fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1; else /* For Gen-IIe - read FIS interrupt cause. */ fisic = ATA_INL(ch->r_mem, SATA_FISIC); -//device_printf(dev, "FISIC %08x\n", fisic); } if (selfdis) ch->curr_mode = MVS_EDMA_UNKNOWN; @@ -745,7 +749,6 @@ mvs_ch_intr(void *data) } } } -//device_printf(dev, "err slot %d port %d\n", ccs, port); mvs_requeue_frozen(dev); for (i = 0; i < MVS_MAX_SLOTS; i++) { /* XXX: reqests in loading state. */ @@ -771,7 +774,8 @@ mvs_ch_intr(void *data) ch->fatalerr = 1; } } else if (iec & 0xfc1e9000) { - if (ch->numtslots == 0 && i != ccs && port != -2) + if (ch->numtslots == 0 && + i != ccs && port != -2) et = MVS_ERR_INNOCENT; else et = MVS_ERR_SATA; @@ -823,8 +827,6 @@ mvs_legacy_intr(device_t dev) /* Clear interrupt and get status. */ status = mvs_getstatus(dev, 1); -// device_printf(dev, "Legacy intr status %02x\n", -// status); if (slot->state < MVS_SLOT_RUNNING) return; port = ccb->ccb_h.target_id & 0x0f; @@ -867,7 +869,8 @@ mvs_legacy_intr(device_t dev) /* If data write command - put them */ if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { - device_printf(dev, "timeout waiting for write DRQ\n"); + device_printf(dev, + "timeout waiting for write DRQ\n"); et = MVS_ERR_TIMEOUT; goto end_finished; } @@ -890,19 +893,18 @@ mvs_legacy_intr(device_t dev) ATA_OUTL(ch->r_mem, DMA_C, 0); goto end_finished; } else { /* ATAPI PIO */ - length = ATA_INB(ch->r_mem,ATA_CYL_LSB) | (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8); + length = ATA_INB(ch->r_mem,ATA_CYL_LSB) | + (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8); ireason = ATA_INB(ch->r_mem,ATA_IREASON); -//device_printf(dev, "status %02x, ireason %02x, length %d\n", status, ireason, length); switch ((ireason & (ATA_I_CMD | ATA_I_IN)) | (status & ATA_S_DRQ)) { case ATAPI_P_CMDOUT: -device_printf(dev, "ATAPI CMDOUT\n"); + device_printf(dev, "ATAPI CMDOUT\n"); /* Return wait for interrupt */ return; case ATAPI_P_WRITE: -//device_printf(dev, "ATAPI WRITE\n"); if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { device_printf(dev, "trying to write on read buffer\n"); et = MVS_ERR_TFE; @@ -920,7 +922,6 @@ device_printf(dev, "ATAPI CMDOUT\n"); return; case ATAPI_P_READ: -//device_printf(dev, "ATAPI READ\n"); if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { device_printf(dev, "trying to read on write buffer\n"); et = MVS_ERR_TFE; @@ -937,7 +938,6 @@ device_printf(dev, "ATAPI CMDOUT\n"); return; case ATAPI_P_DONEDRQ: -device_printf(dev, "ATAPI DONEDRQ\n"); device_printf(dev, "WARNING - DONEDRQ non conformant device\n"); if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { @@ -958,13 +958,13 @@ device_printf(dev, "ATAPI DONEDRQ\n"); case ATAPI_P_ABORT: case ATAPI_P_DONE: -//device_printf(dev, "ATAPI ABORT/DONE\n"); if (status & (ATA_S_ERROR | ATA_S_DWF)) et = MVS_ERR_TFE; goto end_finished; default: - device_printf(dev, "unknown transfer phase (status %02x, ireason %02x)\n", + device_printf(dev, "unknown transfer phase" + " (status %02x, ireason %02x)\n", status, ireason); et = MVS_ERR_TFE; } @@ -1266,8 +1266,6 @@ mvs_legacy_execute_transaction(struct mv ch->rslots |= (1 << slot->slot); ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); if (ccb->ccb_h.func_code == XPT_ATA_IO) { -// device_printf(dev, "%d Legacy command %02x size %d\n", -// port, ccb->ataio.cmd.command, ccb->ataio.dxfer_len); mvs_tfd_write(dev, ccb); /* Device reset doesn't interrupt. */ if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) { @@ -1287,7 +1285,8 @@ mvs_legacy_execute_transaction(struct mv /* If data write command - output the data */ if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { - device_printf(dev, "timeout waiting for write DRQ\n"); + device_printf(dev, + "timeout waiting for write DRQ\n"); mvs_end_transaction(slot, MVS_ERR_TIMEOUT); return; } @@ -1296,9 +1295,6 @@ mvs_legacy_execute_transaction(struct mv ch->transfersize / 2); } } else { -// device_printf(dev, "%d ATAPI command %02x size %d dma %d\n", -// port, ccb->csio.cdb_io.cdb_bytes[0], ccb->csio.dxfer_len, -// ch->basic_dma); ch->donecount = 0; ch->transfersize = min(ccb->csio.dxfer_len, ch->curr[port].bytecount); @@ -1331,7 +1327,8 @@ mvs_legacy_execute_transaction(struct mv DELAY(20); } if (timeout <= 0) { - device_printf(dev, "timeout waiting for ATAPI command ready\n"); + device_printf(dev, + "timeout waiting for ATAPI command ready\n"); mvs_end_transaction(slot, MVS_ERR_TIMEOUT); return; } @@ -1371,8 +1368,6 @@ mvs_execute_transaction(struct mvs_slot int port = ccb->ccb_h.target_id & 0x0f; int i; -// device_printf(dev, "%d EDMA command %02x size %d slot %d tag %d\n", -// port, ccb->ataio.cmd.command, ccb->ataio.dxfer_len, slot->slot, slot->tag); /* Get address of the prepared EPRD */ eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot); /* Prepare CRQB. Gen IIe uses different CRQB format. */ @@ -1554,7 +1549,6 @@ mvs_end_transaction(struct mvs_slot *slo union ccb *ccb = slot->ccb; int lastto; -//device_printf(dev, "cmd done status %d\n", et); bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, BUS_DMASYNC_POSTWRITE); /* Read result registers to the result struct @@ -1792,7 +1786,8 @@ mvs_process_read_log(device_t dev, union if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) device_printf(dev, "Error while READ LOG EXT\n"); else if ((data[0] & 0x80) == 0) { - device_printf(dev, "Non-queued command error in READ LOG EXT\n"); + device_printf(dev, + "Non-queued command error in READ LOG EXT\n"); } for (i = 0; i < MVS_MAX_SLOTS; i++) { if (!ch->hold[i]) Modified: head/sys/dev/mvs/mvs_pci.c ============================================================================== --- head/sys/dev/mvs/mvs_pci.c Wed Oct 20 06:38:54 2010 (r214098) +++ head/sys/dev/mvs/mvs_pci.c Wed Oct 20 07:22:34 2010 (r214099) @@ -339,7 +339,6 @@ mvs_intr(void *data) u_int32_t ic, aic; ic = ATA_INL(ctlr->r_mem, CHIP_MIC); -//device_printf(ctlr->dev, "irq MIC:%08x\n", ic); if (ctlr->msi) { /* We have to to mask MSI during processing. */ mtx_lock(&ctlr->mtx); Modified: head/sys/dev/mvs/mvs_soc.c ============================================================================== --- head/sys/dev/mvs/mvs_soc.c Wed Oct 20 06:38:54 2010 (r214098) +++ head/sys/dev/mvs/mvs_soc.c Wed Oct 20 07:22:34 2010 (r214099) @@ -295,7 +295,6 @@ mvs_intr(void *data) u_int32_t ic, aic; ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); -//device_printf(ctlr->dev, "irq MIC:%08x\n", ic); if ((ic & IC_HC0) == 0) return; /* Acknowledge interrupts of this HC. */
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