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Date:      Wed, 26 Dec 2018 09:33:26 +0000 (UTC)
From:      Andrew Rybchenko <arybchik@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org
Subject:   svn commit: r342480 - in stable/10/sys/dev/sfxge: . common
Message-ID:  <201812260933.wBQ9XQw8001146@repo.freebsd.org>
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Author: arybchik
Date: Wed Dec 26 09:33:26 2018
New Revision: 342480
URL: https://svnweb.freebsd.org/changeset/base/342480

Log:
  MFC r340767
  
  sfxge(4): limit max TXQ size on Medford to 2048
  
  Queues with 4096 descriptors are not supported as the top bit is used
  for vfifo stuffing.
  
  Submitted by:   Mark Spender <mspender at solarflare.com>
  Sponsored by:   Solarflare Communications, Inc.
  Differential Revision:  https://reviews.freebsd.org/D8948

Modified:
  stable/10/sys/dev/sfxge/common/ef10_tx.c   (contents, props changed)
  stable/10/sys/dev/sfxge/common/efx.h
  stable/10/sys/dev/sfxge/common/efx_tx.c
  stable/10/sys/dev/sfxge/common/hunt_nic.c
  stable/10/sys/dev/sfxge/common/medford_nic.c
  stable/10/sys/dev/sfxge/common/siena_nic.c
  stable/10/sys/dev/sfxge/sfxge.c
Directory Properties:
  stable/10/   (props changed)

Modified: stable/10/sys/dev/sfxge/common/ef10_tx.c
==============================================================================
--- stable/10/sys/dev/sfxge/common/ef10_tx.c	Wed Dec 26 09:32:30 2018	(r342479)
+++ stable/10/sys/dev/sfxge/common/ef10_tx.c	Wed Dec 26 09:33:26 2018	(r342480)
@@ -67,7 +67,7 @@ efx_mcdi_init_txq(
 	efx_rc_t rc;
 
 	EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
-	    EFX_TXQ_NBUFS(EFX_TXQ_MAXNDESCS(&enp->en_nic_cfg)));
+	    EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));
 
 	npages = EFX_TXQ_NBUFS(size);
 	if (npages > MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM) {

Modified: stable/10/sys/dev/sfxge/common/efx.h
==============================================================================
--- stable/10/sys/dev/sfxge/common/efx.h	Wed Dec 26 09:32:30 2018	(r342479)
+++ stable/10/sys/dev/sfxge/common/efx.h	Wed Dec 26 09:33:26 2018	(r342480)
@@ -1105,6 +1105,7 @@ typedef struct efx_nic_cfg_s {
 	uint32_t		enc_evq_limit;
 	uint32_t		enc_txq_limit;
 	uint32_t		enc_rxq_limit;
+	uint32_t		enc_txq_max_ndescs;
 	uint32_t		enc_buftbl_limit;
 	uint32_t		enc_piobuf_limit;
 	uint32_t		enc_piobuf_size;
@@ -1974,12 +1975,6 @@ efx_tx_init(
 extern		void
 efx_tx_fini(
 	__in	efx_nic_t *enp);
-
-#define	EFX_BUG35388_WORKAROUND(_encp)					\
-	(((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
-
-#define	EFX_TXQ_MAXNDESCS(_encp)					\
-	((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
 
 #define	EFX_TXQ_MINNDESCS		512
 

Modified: stable/10/sys/dev/sfxge/common/efx_tx.c
==============================================================================
--- stable/10/sys/dev/sfxge/common/efx_tx.c	Wed Dec 26 09:32:30 2018	(r342479)
+++ stable/10/sys/dev/sfxge/common/efx_tx.c	Wed Dec 26 09:33:26 2018	(r342480)
@@ -911,7 +911,7 @@ siena_tx_qcreate(
 	    (1 << FRF_AZ_TX_DESCQ_LABEL_WIDTH));
 	EFSYS_ASSERT3U(label, <, EFX_EV_TX_NLABELS);
 
-	EFSYS_ASSERT(ISP2(EFX_TXQ_MAXNDESCS(encp)));
+	EFSYS_ASSERT(ISP2(encp->enc_txq_max_ndescs));
 	EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS));
 
 	if (!ISP2(n) || (n < EFX_TXQ_MINNDESCS) || (n > EFX_EVQ_MAXNEVS)) {
@@ -923,7 +923,7 @@ siena_tx_qcreate(
 		goto fail2;
 	}
 	for (size = 0;
-	    (1 << size) <= (EFX_TXQ_MAXNDESCS(encp) / EFX_TXQ_MINNDESCS);
+	    (1 << size) <= (int)(encp->enc_txq_max_ndescs / EFX_TXQ_MINNDESCS);
 	    size++)
 		if ((1 << size) == (int)(n / EFX_TXQ_MINNDESCS))
 			break;

Modified: stable/10/sys/dev/sfxge/common/hunt_nic.c
==============================================================================
--- stable/10/sys/dev/sfxge/common/hunt_nic.c	Wed Dec 26 09:32:30 2018	(r342479)
+++ stable/10/sys/dev/sfxge/common/hunt_nic.c	Wed Dec 26 09:33:26 2018	(r342480)
@@ -318,6 +318,12 @@ hunt_board_cfg(
 	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
 	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
 
+	/*
+	 * The workaround for bug35388 uses the top bit of transmit queue
+	 * descriptor writes, preventing the use of 4096 descriptor TXQs.
+	 */
+	encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
+
 	encp->enc_buftbl_limit = 0xFFFFFFFF;
 
 	encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;

Modified: stable/10/sys/dev/sfxge/common/medford_nic.c
==============================================================================
--- stable/10/sys/dev/sfxge/common/medford_nic.c	Wed Dec 26 09:32:30 2018	(r342479)
+++ stable/10/sys/dev/sfxge/common/medford_nic.c	Wed Dec 26 09:33:26 2018	(r342480)
@@ -315,6 +315,13 @@ medford_board_cfg(
 	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
 	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
 
+	/*
+	 * The maximum supported transmit queue size is 2048. TXQs with 4096
+	 * descriptors are not supported as the top bit is used for vfifo
+	 * stuffing.
+	 */
+	encp->enc_txq_max_ndescs = 2048;
+
 	encp->enc_buftbl_limit = 0xFFFFFFFF;
 
 	encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;

Modified: stable/10/sys/dev/sfxge/common/siena_nic.c
==============================================================================
--- stable/10/sys/dev/sfxge/common/siena_nic.c	Wed Dec 26 09:32:30 2018	(r342479)
+++ stable/10/sys/dev/sfxge/common/siena_nic.c	Wed Dec 26 09:33:26 2018	(r342480)
@@ -156,6 +156,8 @@ siena_board_cfg(
 	encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
 	encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
 
+	encp->enc_txq_max_ndescs = 4096;
+
 	encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
 	    (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
 	    (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));

Modified: stable/10/sys/dev/sfxge/sfxge.c
==============================================================================
--- stable/10/sys/dev/sfxge/sfxge.c	Wed Dec 26 09:32:30 2018	(r342479)
+++ stable/10/sys/dev/sfxge/sfxge.c	Wed Dec 26 09:33:26 2018	(r342480)
@@ -756,10 +756,10 @@ sfxge_create(struct sfxge_softc *sc)
 
 	if (!ISP2(sfxge_tx_ring_entries) ||
 	    (sfxge_tx_ring_entries < EFX_TXQ_MINNDESCS) ||
-	    (sfxge_tx_ring_entries > EFX_TXQ_MAXNDESCS(efx_nic_cfg_get(enp)))) {
+	    (sfxge_tx_ring_entries > efx_nic_cfg_get(enp)->enc_txq_max_ndescs)) {
 		log(LOG_ERR, "%s=%d must be power of 2 from %u to %u",
 		    SFXGE_PARAM_TX_RING, sfxge_tx_ring_entries,
-		    EFX_TXQ_MINNDESCS, EFX_TXQ_MAXNDESCS(efx_nic_cfg_get(enp)));
+		    EFX_TXQ_MINNDESCS, efx_nic_cfg_get(enp)->enc_txq_max_ndescs);
 		error = EINVAL;
 		goto fail_tx_ring_entries;
 	}

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