Date: Thu, 12 Feb 2015 19:45:07 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r278631 - in stable/10/sys/arm: arm include Message-ID: <201502121945.t1CJj78t064149@svn.freebsd.org>
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Author: ian Date: Thu Feb 12 19:45:07 2015 New Revision: 278631 URL: https://svnweb.freebsd.org/changeset/base/278631 Log: MFC r272209, r272300, r276212, r276213: Add machine/sysreg.h to simplify accessing the system control coprocessor registers and use it in the ARMv7 CPU functions. Add macros for asm barrier instructions with arch-specific implementations. Define only the CP15 register operations that are valid for the architecture. Added: stable/10/sys/arm/include/sysreg.h - copied, changed from r272209, head/sys/arm/include/sysreg.h Modified: stable/10/sys/arm/arm/cpufunc_asm_armv7.S stable/10/sys/arm/include/asm.h Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/arm/cpufunc_asm_armv7.S ============================================================================== --- stable/10/sys/arm/arm/cpufunc_asm_armv7.S Thu Feb 12 19:35:46 2015 (r278630) +++ stable/10/sys/arm/arm/cpufunc_asm_armv7.S Thu Feb 12 19:45:07 2015 (r278631) @@ -33,6 +33,8 @@ #include <machine/asm.h> __FBSDID("$FreeBSD$"); +#include <machine/sysreg.h> + .cpu cortex-a8 .Lcoherency_level: @@ -70,12 +72,12 @@ ENTRY(armv7_setttb) dsb orr r0, r0, #PT_ATTR - mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */ + mcr CP15_TTBR0(r0) isb #ifdef SMP - mcr p15, 0, r0, c8, c3, 0 /* invalidate I+D TLBs Inner Shareable*/ + mcr CP15_TLBIALLIS #else - mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ + mcr CP15_TLBIALL #endif dsb isb @@ -85,11 +87,11 @@ END(armv7_setttb) ENTRY(armv7_tlb_flushID) dsb #ifdef SMP - mcr p15, 0, r0, c8, c3, 0 /* flush Unified TLB all entries Inner Shareable */ - mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */ + mcr CP15_TLBIALLIS + mcr CP15_BPIALLIS #else - mcr p15, 0, r0, c8, c7, 0 /* flush Unified TLB all entries */ - mcr p15, 0, r0, c7, c5, 6 /* flush BTB */ + mcr CP15_TLBIALL + mcr CP15_BPIALL #endif dsb isb @@ -100,11 +102,11 @@ ENTRY(armv7_tlb_flushID_SE) ldr r1, .Lpage_mask bic r0, r0, r1 #ifdef SMP - mcr p15, 0, r0, c8, c3, 3 /* flush Unified TLB single entry Inner Shareable */ - mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */ + mcr CP15_TLBIMVAAIS(r0) + mcr CP15_BPIALLIS #else - mcr p15, 0, r0, c8, c7, 1 /* flush Unified TLB single entry */ - mcr p15, 0, r0, c7, c5, 6 /* flush BTB */ + mcr CP15_TLBIMVA(r0) + mcr CP15_BPIALL #endif dsb isb @@ -149,7 +151,7 @@ Loop3: orr r6, r6, r7, lsl r2 /* Clean and invalidate data cache by way/index */ - mcr p15, 0, r6, c7, c14, 2 + mcr CP15_DCCISW(r6) subs r9, r9, #1 bge Loop3 subs r7, r7, #1 @@ -168,9 +170,9 @@ ENTRY(armv7_idcache_wbinv_all) stmdb sp!, {lr} bl armv7_dcache_wbinv_all #ifdef SMP - mcr p15, 0, r0, c7, c1, 0 /* Invalidate all I caches to PoU (ICIALLUIS) */ + mcr CP15_ICIALLUIS #else - mcr p15, 0, r0, c7, c5, 0 /* Invalidate all I caches to PoU (ICIALLU) */ + mcr CP15_ICIALLU #endif dsb isb @@ -191,7 +193,7 @@ ENTRY(armv7_dcache_wb_range) add r1, r1, r2 bic r0, r0, r3 .Larmv7_wb_next: - mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ + mcr CP15_DCCMVAC(r0) add r0, r0, ip subs r1, r1, ip bhi .Larmv7_wb_next @@ -206,7 +208,7 @@ ENTRY(armv7_dcache_wbinv_range) add r1, r1, r2 bic r0, r0, r3 .Larmv7_wbinv_next: - mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */ + mcr CP15_DCCIMVAC(r0) add r0, r0, ip subs r1, r1, ip bhi .Larmv7_wbinv_next @@ -225,7 +227,7 @@ ENTRY(armv7_dcache_inv_range) add r1, r1, r2 bic r0, r0, r3 .Larmv7_inv_next: - mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */ + mcr CP15_DCIMVAC(r0) add r0, r0, ip subs r1, r1, ip bhi .Larmv7_inv_next @@ -240,8 +242,8 @@ ENTRY(armv7_idcache_wbinv_range) add r1, r1, r2 bic r0, r0, r3 .Larmv7_id_wbinv_next: - mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ - mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */ + mcr CP15_ICIMVAU(r0) + mcr CP15_DCCIMVAC(r0) add r0, r0, ip subs r1, r1, ip bhi .Larmv7_id_wbinv_next @@ -252,9 +254,9 @@ END(armv7_idcache_wbinv_range) ENTRY_NP(armv7_icache_sync_all) #ifdef SMP - mcr p15, 0, r0, c7, c1, 0 /* Invalidate all I cache to PoU Inner Shareable */ + mcr CP15_ICIALLUIS #else - mcr p15, 0, r0, c7, c5, 0 /* Invalidate all I cache to PoU (ICIALLU) */ + mcr CP15_ICIALLU #endif isb /* instruction synchronization barrier */ dsb /* data synchronization barrier */ @@ -264,8 +266,8 @@ END(armv7_icache_sync_all) ENTRY_NP(armv7_icache_sync_range) ldr ip, .Larmv7_line_size .Larmv7_sync_next: - mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ - mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ + mcr CP15_ICIMVAU(r0) + mcr CP15_DCCMVAC(r0) add r0, r0, ip subs r1, r1, ip bhi .Larmv7_sync_next @@ -283,13 +285,13 @@ END(armv7_cpu_sleep) ENTRY(armv7_context_switch) dsb orr r0, r0, #PT_ATTR - - mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ + + mcr CP15_TTBR0(r0) isb #ifdef SMP - mcr p15, 0, r0, c8, c3, 0 /* and flush the I+D tlbs Inner Sharable */ + mcr CP15_TLBIALLIS #else - mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ + mcr CP15_TLBIALL #endif dsb isb @@ -309,12 +311,12 @@ ENTRY(armv7_sev) END(armv7_sev) ENTRY(armv7_auxctrl) - mrc p15, 0, r2, c1, c0, 1 + mrc CP15_ACTLR(r2) bic r3, r2, r0 /* Clear bits */ eor r3, r3, r1 /* XOR bits */ teq r2, r3 - mcrne p15, 0, r3, c1, c0, 1 + mcrne CP15_ACTLR(r3) mov r0, r2 RET END(armv7_auxctrl) @@ -325,8 +327,8 @@ END(armv7_auxctrl) */ ENTRY(armv7_idcache_inv_all) mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 @ set cache level to L1 - mrc p15, 1, r0, c0, c0, 0 @ read CCSIDR + mcr CP15_CSSELR(r0) @ set cache level to L1 + mrc CP15_CCSIDR(r0) ubfx r2, r0, #13, #15 @ get num sets - 1 from CCSIDR ubfx r3, r0, #3, #10 @ get numways - 1 from CCSIDR @@ -345,7 +347,7 @@ ENTRY(armv7_idcache_inv_all) mov r2, ip @ r2 now contains set way decr /* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */ -1: mcr p15, 0, r3, c7, c6, 2 @ invalidate line +1: mcr CP15_DCISW(r3) @ invalidate line movs r0, r3 @ get current way/set beq 2f @ at 0 means we are done. movs r0, r0, lsl #10 @ clear way bits leaving only set bits @@ -355,7 +357,7 @@ ENTRY(armv7_idcache_inv_all) 2: dsb @ wait for stores to finish mov r0, #0 @ and ... - mcr p15, 0, r0, c7, c5, 0 @ invalidate instruction+branch cache + mcr CP15_ICIALLU @ invalidate instruction+branch cache isb @ instruction sync barrier bx lr @ return END(armv7_idcache_inv_all) Modified: stable/10/sys/arm/include/asm.h ============================================================================== --- stable/10/sys/arm/include/asm.h Thu Feb 12 19:35:46 2015 (r278630) +++ stable/10/sys/arm/include/asm.h Thu Feb 12 19:45:07 2015 (r278631) @@ -39,6 +39,7 @@ #ifndef _MACHINE_ASM_H_ #define _MACHINE_ASM_H_ #include <sys/cdefs.h> +#include <machine/sysreg.h> #define _C_LABEL(x) x #define _ASM_LABEL(x) x @@ -221,4 +222,18 @@ # define RETc(c) mov##c pc, lr #endif +#if __ARM_ARCH >= 7 +#define ISB isb +#define DSB dsb +#define DMB dmb +#elif __ARM_ARCH == 6 +#define ISB mcr CP15_CP15ISB +#define DSB mcr CP15_CP15DSB +#define DMB mcr CP15_CP15DMB +#else +#define ISB mcr CP15_CP15ISB +#define DSB mcr CP15_CP15DSB /* DSB and DMB are the */ +#define DMB mcr CP15_CP15DSB /* same prior to v6.*/ +#endif + #endif /* !_MACHINE_ASM_H_ */ Copied and modified: stable/10/sys/arm/include/sysreg.h (from r272209, head/sys/arm/include/sysreg.h) ============================================================================== --- head/sys/arm/include/sysreg.h Sat Sep 27 09:57:34 2014 (r272209, copy source) +++ stable/10/sys/arm/include/sysreg.h Thu Feb 12 19:45:07 2015 (r278631) @@ -34,6 +34,8 @@ #ifndef MACHINE_SYSREG_H #define MACHINE_SYSREG_H +#include <machine/acle-compat.h> + /* * CP15 C0 registers */ @@ -97,12 +99,13 @@ #if __ARM_ARCH >= 6 /* From ARMv6: */ #define CP15_IFSR(rr) p15, 0, rr, c5, c0, 1 /* Instruction Fault Status Register */ +#endif +#if __ARM_ARCH >= 7 /* From ARMv7: */ #define CP15_ADFSR(rr) p15, 0, rr, c5, c1, 0 /* Auxiliary Data Fault Status Register */ #define CP15_AIFSR(rr) p15, 0, rr, c5, c1, 1 /* Auxiliary Instruction Fault Status Register */ #endif - /* * CP15 C6 registers */ @@ -116,7 +119,7 @@ /* * CP15 C7 registers */ -#if __ARM_ARCH >= 6 +#if __ARM_ARCH >= 7 && defined(SMP) /* From ARMv7: */ #define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */ #define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */ @@ -126,14 +129,14 @@ #define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */ #define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */ -#if __ARM_ARCH >= 6 +#if __ARM_ARCH == 6 /* Deprecated in ARMv7 */ #define CP15_CP15ISB p15, 0, r0, c7, c5, 4 /* ISB */ #endif #define CP15_BPIALL p15, 0, r0, c7, c5, 6 /* Branch predictor invalidate all */ #define CP15_BPIMVA p15, 0, rr, c7, c5, 7 /* Branch predictor invalidate by MVA */ -#if __ARM_ARCH >= 6 +#if __ARM_ARCH == 6 /* Only ARMv6: */ #define CP15_DCIALL p15, 0, r0, c7, c6, 0 /* Data cache invalidate all */ #endif @@ -145,7 +148,7 @@ #define CP15_ATS1CUR(rr) p15, 0, rr, c7, c8, 2 /* Stage 1 Current state unprivileged read */ #define CP15_ATS1CUW(rr) p15, 0, rr, c7, c8, 3 /* Stage 1 Current state unprivileged write */ -#if __ARM_ARCH >= 6 +#if __ARM_ARCH >= 7 /* From ARMv7: */ #define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */ #define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */ @@ -153,24 +156,24 @@ #define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged write */ #endif -#if __ARM_ARCH >= 6 +#if __ARM_ARCH == 6 /* Only ARMv6: */ #define CP15_DCCALL p15, 0, r0, c7, c10, 0 /* Data cache clean all */ #endif #define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */ #define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */ -#if __ARM_ARCH >= 6 +#if __ARM_ARCH == 6 /* Only ARMv6: */ #define CP15_CP15DSB p15, 0, r0, c7, c10, 4 /* DSB */ #define CP15_CP15DMB p15, 0, r0, c7, c10, 5 /* DMB */ #endif -#if __ARM_ARCH >= 6 +#if __ARM_ARCH >= 7 /* From ARMv7: */ #define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */ #endif -#if __ARM_ARCH >= 6 +#if __ARM_ARCH == 6 /* Only ARMv6: */ #define CP15_DCCIALL p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */ #endif @@ -180,7 +183,7 @@ /* * CP15 C8 registers */ -#if __ARM_ARCH >= 6 +#if __ARM_ARCH >= 7 && defined(SMP) /* From ARMv7: */ #define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */ #define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */ @@ -227,4 +230,9 @@ #define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */ #define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */ +/* + * CP15 C15 registers + */ +#define CP15_CBAR(rr) p15, 4, rr, c15, c0, 0 /* Configuration Base Address Register */ + #endif /* !MACHINE_SYSREG_H */
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