Date: Mon, 28 Apr 2025 16:04:02 GMT From: Warner Losh <imp@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 77be1f2fa6a1 - main - =?utf-8?Q?Fix TXFIFO register write and timeout message Changes: - Fixed incorrect = Message-ID: <202504281604.53SG421W039084@gitrepo.freebsd.org>
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register write for TXFIFO invalidation (FSPI_IPRXFCR =E2=86=92 FSPI_IPTXF= CR). - Corrected error message for TXFIFO wait timeout (FSPI_INTR_IPRXWA = =E2=86=92 FSPI_INTR_IPTXWE). - Corrected comment for TXFIFO available (RX= FIFO -> TXFIFO)?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: imp X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 77be1f2fa6a18afc0d9111b2e4880fd4bacca02a Auto-Submitted: auto-generated The branch main has been updated by imp: URL: https://cgit.FreeBSD.org/src/commit/?id=77be1f2fa6a18afc0d9111b2e4880fd4bacca02a commit 77be1f2fa6a18afc0d9111b2e4880fd4bacca02a Author: Premal Gajjar <premal.gajjar@einfochips.com> AuthorDate: 2025-02-24 13:46:13 +0000 Commit: Warner Losh <imp@FreeBSD.org> CommitDate: 2025-04-28 16:02:50 +0000 Fix TXFIFO register write and timeout message Changes: - Fixed incorrect register write for TXFIFO invalidation (FSPI_IPRXFCR → FSPI_IPTXFCR). - Corrected error message for TXFIFO wait timeout (FSPI_INTR_IPRXWA → FSPI_INTR_IPTXWE). - Corrected comment for TXFIFO available (RXFIFO -> TXFIFO) Reviewed-by: imp@FreeBSD.org Reviewed-by: jlduran@FreeBSD.org Pull-request: https://github.com/freebsd/freebsd-src/pull/1604 --- sys/dev/flash/flexspi/flex_spi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sys/dev/flash/flexspi/flex_spi.c b/sys/dev/flash/flexspi/flex_spi.c index 9382b237ee71..44246f4b1c2d 100644 --- a/sys/dev/flash/flexspi/flex_spi.c +++ b/sys/dev/flash/flexspi/flex_spi.c @@ -329,20 +329,20 @@ flex_spi_write_txfifo(struct flex_spi_softc *sc, uint8_t *buf, uint8_t size) int i, ret, reg; /* invalid the TXFIFO */ - write_reg(sc, FSPI_IPRXFCR, FSPI_IPTXFCR_CLR); + write_reg(sc, FSPI_IPTXFCR, FSPI_IPTXFCR_CLR); /* * Default value of water mark level is 8 bytes, hence in single * read request controller can read max 8 bytes of data. */ for (i = 0; i < size; i += 4) { - /* Wait for RXFIFO available */ + /* Wait for TXFIFO available */ if (i % 8 == 0) { ret = reg_read_poll_tout(sc, FSPI_INTR, FSPI_INTR_IPTXWE, 1, 50000, 1); if (ret) device_printf(sc->dev, - "timed out waiting for FSPI_INTR_IPRXWA\n"); + "timed out waiting for FSPI_INTR_IPTXWE\n"); } if (size >= (i + 4))help
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