Date: Sat, 1 May 2010 16:36:14 +0000 (UTC) From: Warner Losh <imp@FreeBSD.org> To: cvs-src-old@freebsd.org Subject: cvs commit: src/sys/conf NOTES options src/sys/dev/ath/ath_hal/ar5212 ar5212_reset.c Message-ID: <201005011637.o41GbBvt037188@repoman.freebsd.org>
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imp 2010-05-01 16:36:14 UTC
FreeBSD src repository
Modified files:
sys/conf NOTES options
sys/dev/ath/ath_hal/ar5212 ar5212_reset.c
Log:
SVN rev 207472 on 2010-05-01 16:36:14Z by imp
The Atheros AR71xx CPUs, when paired with the AR5212 parts, has a bug
that generates a fatal bus trap. Normally, the chips are setup to do
128 byte DMA bursts, but when on this CPU, they can only safely due
4-byte DMA bursts due to this bug. Details of the exact nature of the
bug are sketchy, but some can be found at
https://forum.openwrt.org/viewtopic.php?pid=70060 on pages 4, 5 and 6.
There's a small performance penalty associated with this workaround,
so it is only enabled when needed on the Atheros AR71xx platforms.
Unfortunately, this condition is impossible to detect at runtime
without MIPS specific ifdefs. Rather than cast an overly-broad net
like Linux/OpenWRT dues (which enables this workaround all the time on
MIPS32 platforms), we put this option in the kernel for just the
affected machines. Sam didn't like this aspect of the patch when he
reviewed it, and I'd love to hear sane proposals on how to fix it :)
Reviewed by: sam@
Revision Changes Path
1.1582 +9 -0 src/sys/conf/NOTES
1.702 +1 -0 src/sys/conf/options
1.10 +8 -0 src/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c
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