Date: Wed, 26 May 2010 09:50:10 +0000 (UTC) From: Rafal Jaworowski <raj@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r208561 - head/sys/boot/fdt/dts Message-ID: <201005260950.o4Q9oAZx006019@svn.freebsd.org>
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Author: raj Date: Wed May 26 09:50:09 2010 New Revision: 208561 URL: http://svn.freebsd.org/changeset/base/208561 Log: Initial device tree source (DTS) files for Marvell ARM systems: o DB-88F5182 o DB-88F5281 o DB-88F6281 o DB-78100 o SheevaPlug This also includes device tree bindings definitions for some newly introduced nodes (mpp, gpio). Reviewed by: imp Sponsored by: The FreeBSD Foundation Added: head/sys/boot/fdt/dts/bindings-gpio.txt (contents, props changed) head/sys/boot/fdt/dts/bindings-mpp.txt (contents, props changed) head/sys/boot/fdt/dts/db78100.dts (contents, props changed) head/sys/boot/fdt/dts/db88f5182.dts (contents, props changed) head/sys/boot/fdt/dts/db88f5281.dts (contents, props changed) head/sys/boot/fdt/dts/db88f6281.dts (contents, props changed) head/sys/boot/fdt/dts/sheevaplug.dts (contents, props changed) Added: head/sys/boot/fdt/dts/bindings-gpio.txt ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/bindings-gpio.txt Wed May 26 09:50:09 2010 (r208561) @@ -0,0 +1,101 @@ +$FreeBSD$ + +GPIO configuration. +=================== + +1. Properties for GPIO Controllers + +1.1 #gpio-cells + +Property: #gpio-cells + +Value type: <u32> + +Description: The #gpio-cells property defines the number of cells required + to encode a gpio specifier. + + +1.2 gpio-controller + +Property: gpio-controller + +Value type: <empty> + +Description: The presence of a gpio-controller property defines a node as a + GPIO controller node. + + +1.3 pin-count + +Property: pin-count + +Value type: <u32> + +Description: The pin-count property defines the number of GPIO pins. + + +1.4 Example + + GPIO: gpio@10100 { + #gpio-cells = <3>; + compatible = "mrvl,gpio"; + reg = <0x10100 0x20>; + gpio-controller; + interrupts = <6 7 8 9>; + interrupt-parent = <&PIC>; + pin-count = <50> + }; + +2. Properties for GPIO consumer nodes. + +2.1 gpios + +Property: gpios + +Value type: <prop-encoded-array> encoded as arbitrary number of GPIO + specifiers. + +Description: The gpios property of a device node defines the GPIO or GPIOs + that are used by the device. The value of the gpios property + consists of an arbitrary number of GPIO specifiers. + + The first cell of the GPIO specifier is phandle of the node's + parent GPIO controller and remaining cells are defined by the + binding describing the GPIO parent, typically include + information like pin number, direction and various flags. + +Example: + gpios = <&GPIO 0 1 0 /* GPIO[0]: IN, NONE */ + &GPIO 1 2 0>; /* GPIO[1]: OUT, NONE */ + + +3. "mrvl,gpio" controller GPIO specifier + + <phandle pin dir flags> + + +pin: 0-MAX GPIO pin number. + +dir: + 1 IN Input direction. + 2 OUT Output direction. + +flags: + 0x0000---- IN_NONE + 0x0001---- IN_POL_LOW Polarity low (inverted input value. + 0x0002---- IN_IRQ_EDGE Interrupt, edge triggered. + 0x0004---- IN_IRQ_LEVEL Interrupt, level triggered. + + 0x----0000 OUT_NONE + 0x----0001 OUT_BLINK Blink on the pin. + 0x----0002 OUT_OPEN_DRAIN Open drain output line. + 0x----0004 OUT_OPEN_SRC Open source output line. + + +Example: + gpios = <&GPIO 0 1 0x00000000 /* GPIO[0]: IN */ + &GPIO 1 2 0x00000000 /* GPIO[1]: OUT */ + &GPIO 2 1 0x00020000 /* GPIO[2]: IN, IRQ (edge) */ + &GPIO 3 1 0x00040000 /* GPIO[3]: IN, IRQ (level) */ + ... + &GPIO 10 2 0x00000001>; /* GPIO[10]: OUT, blink */ Added: head/sys/boot/fdt/dts/bindings-mpp.txt ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/bindings-mpp.txt Wed May 26 09:50:09 2010 (r208561) @@ -0,0 +1,50 @@ +$FreeBSD$ + +* Multi purpose pin (MPP) configuration. + +Required properties: + +- pin-map : array of pin configurations. Each pin is defined by 2 cells, + respectively: <pin> <function>. Pins not specified in the pin-map property + are assumed to have default value of <function> = 0, which means GPIO. + + - pin : pin number. + + - function : function ID of the pin according to the assignment tables in + User Manual. Each pin can have many possible functions depending on the + MPP unit incarnation. + +- pin-count: number of the physical MPP connections on the SOC (depending on + the model it can be 24-50, or possibly else in future devices). + +Example: + + mpp@10000 { + #pin-cells = <2>; + compatible = "mrvl,mpp"; + reg = <0x10000 0x34>; + pin-count= <50>; + pin-map = < + 0 1 /* MPP[0]: NF_IO[2] */ + 1 1 /* MPP[1]: NF_IO[3] */ + 2 1 /* MPP[2]: NF_IO[4] */ + 3 1 /* MPP[3]: NF_IO[5] */ + 4 1 /* MPP[4]: NF_IO[6] */ + 5 1 /* MPP[5]: NF_IO[7] */ + 6 1 /* MPP[6]: SYSRST_OUTn */ + 7 2 /* MPP[7]: SPI_SCn */ + 8 1 /* MPP[8]: TW_SDA */ + 9 1 /* MPP[9]: TW_SCK */ + 10 3 /* MPP[10]: UA0_TXD */ + 11 3 /* MPP[11]: UA0_RXD */ + 12 1 /* MPP[12]: SD_CLK */ + 13 1 /* MPP[13]: SD_CMD */ + 14 1 /* MPP[14]: SD_D[0] */ + 15 1 /* MPP[15]: SD_D[1] */ + 16 1 /* MPP[16]: SD_D[2] */ + 17 1 /* MPP[17]: SD_D[3] */ + 18 1 /* MPP[18]: NF_IO[0] */ + 19 1 /* MPP[19]: NF_IO[1] */ + 20 5 /* MPP[20]: SATA1_AC */ + 21 5 >; /* MPP[21]: SATA0_AC */ + }; Added: head/sys/boot/fdt/dts/db78100.dts ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/db78100.dts Wed May 26 09:50:09 2010 (r208561) @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2010 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Semihalf under sponsorship from + * the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Marvell DB-78100 Device Tree Source. + * + * $FreeBSD$ + */ + +/dts-v1/; + +/ { + model = "mrvl,DB-78100"; + compatible = "DB-78100-BP", "DB-78100-BP-A"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + serial0 = &serial0; + serial1 = &serial1; + mpp = &MPP; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "ARM,88FR571"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x4000>; // L1, 16K + i-cache-size = <0x4000>; // L1, 16K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; // 512M at 0x0 + }; + + localbus@f1000000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "mrvl,lbc"; + win-count = <14>; + + /* This reflects CPU decode windows setup. */ + ranges = <0x0 0x0f 0xf9300000 0x00100000 + 0x1 0x1e 0xfa000000 0x00100000 + 0x2 0x1d 0xfa100000 0x02000000 + 0x3 0x1b 0xfc100000 0x00000400>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x00100000>; + bank-width = <2>; + device-width = <1>; + }; + + led@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "led"; + reg = <0x1 0x0 0x00100000>; + }; + + nor@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x2 0x0 0x02000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@3,0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x3 0x0 0x00100000>; + bank-width = <2>; + device-width = <1>; + }; + }; + + soc78100@f1000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0xf1000000 0x00100000>; + bus-frequency = <0>; + + PIC: pic@20200 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x20200 0x3c>; + compatible = "mrvl,pic"; + }; + + timer@20300 { + compatible = "mrvl,timer"; + reg = <0x20300 0x30>; + interrupts = <8>; + interrupt-parent = <&PIC>; + mrvl,has-wdt; + }; + + MPP: mpp@10000 { + #pin-cells = <2>; + compatible = "mrvl,mpp"; + reg = <0x10000 0x34>; + pin-count = <50>; + pin-map = < + 0 2 /* MPP[0]: GE1_TXCLK */ + 1 2 /* MPP[1]: GE1_TXCTL */ + 2 2 /* MPP[2]: GE1_RXCTL */ + 3 2 /* MPP[3]: GE1_RXCLK */ + 4 2 /* MPP[4]: GE1_TXD[0] */ + 5 2 /* MPP[5]: GE1_TXD[1] */ + 6 2 /* MPP[6]: GE1_TXD[2] */ + 7 2 /* MPP[7]: GE1_TXD[3] */ + 8 2 /* MPP[8]: GE1_RXD[0] */ + 9 2 /* MPP[9]: GE1_RXD[1] */ + 10 2 /* MPP[10]: GE1_RXD[2] */ + 11 2 /* MPP[11]: GE1_RXD[3] */ + 13 3 /* MPP[13]: SYSRST_OUTn */ + 14 3 /* MPP[14]: SATA1_ACTn */ + 15 3 /* MPP[15]: SATA0_ACTn */ + 16 4 /* MPP[16]: UA2_TXD */ + 17 4 /* MPP[17]: UA2_RXD */ + 18 3 /* MPP[18]: <UNKNOWN> */ + 19 3 /* MPP[19]: <UNKNOWN> */ + 20 3 /* MPP[20]: <UNKNOWN> */ + 21 3 /* MPP[21]: <UNKNOWN> */ + 22 4 /* MPP[22]: UA3_TXD */ + 23 4 >; /* MPP[21]: UA3_RXD */ + }; + + GPIO: gpio@10100 { + #gpio-cells = <3>; + compatible = "mrvl,gpio"; + reg = <0x10100 0x20>; + gpio-controller; + interrupts = <56 57 58 59>; + interrupt-parent = <&PIC>; + }; + + rtc@10300 { + compatible = "mrvl,rtc"; + reg = <0x10300 0x08>; + }; + + twsi@11000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mrvl,twsi"; + reg = <0x11000 0x20>; + interrupts = <2>; + interrupt-parent = <&PIC>; + }; + + twsi@11100 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mrvl,twsi"; + reg = <0x11100 0x20>; + interrupts = <3>; + interrupt-parent = <&PIC>; + }; + + enet0: ethernet@72000 { + #address-cells = <1>; + #size-cells = <1>; + model = "V2"; + compatible = "mrvl,ge"; + reg = <0x72000 0x2000>; + ranges = <0x0 0x72000 0x2000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <41 42 43 40 70>; + interrupt-parent = <&PIC>; + phy-handle = <&phy0>; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mrvl,mdio"; + + phy0: ethernet-phy@0 { + reg = <0x8>; + }; + }; + }; + + enet1: ethernet@76000 { + #address-cells = <1>; + #size-cells = <1>; + model = "V2"; + compatible = "mrvl,ge"; + reg = <0x76000 0x2000>; + ranges = <0x0 0x76000 0x2000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <45 46 47 44 70>; + interrupt-parent = <&PIC>; + phy-handle = <&phy0>; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mrvl,mdio"; + + phy0: ethernet-phy@0 { + reg = <0x9>; + }; + }; + }; + + serial0: serial@12000 { + compatible = "ns16550"; + reg = <0x12000 0x20>; + reg-shift = <2>; + clock-frequency = <0>; + interrupts = <12>; + interrupt-parent = <&PIC>; + }; + + serial1: serial@12100 { + compatible = "ns16550"; + reg = <0x12100 0x20>; + reg-shift = <2>; + clock-frequency = <0>; + interrupts = <13>; + interrupt-parent = <&PIC>; + }; + + usb@50000 { + compatible = "mrvl,usb-ehci", "usb-ehci"; + reg = <0x50000 0x1000>; + interrupts = <72 16>; + interrupt-parent = <&PIC>; + }; + + usb@51000 { + compatible = "mrvl,usb-ehci", "usb-ehci"; + reg = <0x51000 0x1000>; + interrupts = <72 17>; + interrupt-parent = <&PIC>; + }; + + usb@52000 { + compatible = "mrvl,usb-ehci", "usb-ehci"; + reg = <0x52000 0x1000>; + interrupts = <72 18>; + interrupt-parent = <&PIC>; + }; + + xor@60000 { + compatible = "mrvl,xor"; + reg = <0x60000 0x1000>; + interrupts = <22 23>; + interrupt-parent = <&PIC>; + }; + + crypto@90000 { + compatible = "mrvl,cesa"; + reg = <0x90000 0x10000>; + interrupts = <19>; + interrupt-parent = <&PIC>; + }; + + sata@a0000 { + compatible = "mrvl,sata"; + reg = <0xa0000 0x6000>; + interrupts = <26>; + interrupt-parent = <&PIC>; + }; + }; + + sram@fd000000 { + compatible = "mrvl,cesa-sram"; + reg = <0xfd000000 0x00100000>; + }; +}; Added: head/sys/boot/fdt/dts/db88f5182.dts ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/db88f5182.dts Wed May 26 09:50:09 2010 (r208561) @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2010 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Semihalf under sponsorship from + * the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Marvell DB-88F5182 Device Tree Source. + * + * $FreeBSD$ + */ + +/dts-v1/; + +/ { + model = "mrvl,DB-88F5182"; + compatible = "DB-88F5182-BP", "DB-88F5182-BP-A"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + serial0 = &serial0; + serial1 = &serial1; + mpp = &MPP; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "ARM,88FR531"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; // 128M at 0x0 + }; + + localbus@f1000000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "mrvl,lbc"; + + /* This reflects CPU decode windows setup. */ + ranges = <0x0 0x0f 0xf9300000 0x00100000 + 0x1 0x1e 0xfa000000 0x00100000 + 0x2 0x1d 0xfa100000 0x02000000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x00100000>; + bank-width = <2>; + device-width = <1>; + }; + + led@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "led"; + reg = <0x1 0x0 0x00100000>; + }; + + nor@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x2 0x0 0x02000000>; + bank-width = <2>; + device-width = <1>; + }; + }; + + soc88f5182@f1000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0xf1000000 0x00100000>; + bus-frequency = <0>; + + PIC: pic@20200 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x20200 0x3c>; + compatible = "mrvl,pic"; + }; + + timer@20300 { + compatible = "mrvl,timer"; + reg = <0x20300 0x30>; + interrupts = <0>; + interrupt-parent = <&PIC>; + mrvl,has-wdt; + }; + + MPP: mpp@10000 { + #pin-cells = <2>; + compatible = "mrvl,mpp"; + reg = <0x10000 0x54>; + pin-count = <20>; + pin-map = < + 0 3 /* MPP[0]: GPIO[0] */ + 2 2 /* MPP[2]: PCI_REQn[3] */ + 3 2 /* MPP[3]: PCI_GNTn[3] */ + 4 2 /* MPP[4]: PCI_REQn[4] */ + 5 2 /* MPP[5]: PCI_GNTn[4] */ + 6 5 /* MPP[6]: SATA0_ACT */ + 7 5 /* MPP[7]: SATA1_ACT */ + 12 5 /* MPP[12]: SATA0_PRESENT */ + 13 5 /* MPP[13]: SATA1_PRESENT */ + 14 4 /* MPP[14]: NAND Flash REn[2] */ + 15 4 /* MPP[15]: NAND Flash WEn[2] */ + 16 0 /* MPP[16]: UA1_RXD */ + 17 0 /* MPP[17]: UA1_TXD */ + 18 0 /* MPP[18]: UA1_CTS */ + 19 0 >; /* MPP[19]: UA1_RTS */ + }; + + GPIO: gpio@10100 { + #gpio-cells = <3>; + compatible = "mrvl,gpio"; + reg = <0x10100 0x20>; + gpio-controller; + interrupts = <6 7 8 9>; + interrupt-parent = <&PIC>; + }; + + twsi@11000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mrvl,twsi"; + reg = <0x11000 0x20>; + interrupts = <43>; + interrupt-parent = <&PIC>; + }; + + enet0: ethernet@72000 { + #address-cells = <1>; + #size-cells = <1>; + model = "V1"; + compatible = "mrvl,ge"; + reg = <0x72000 0x2000>; + ranges = <0x0 0x72000 0x2000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <18 19 20 21 22>; + interrupt-parent = <&PIC>; + }; + + serial0: serial@12000 { + compatible = "ns16550"; + reg = <0x12000 0x20>; + reg-shift = <2>; + clock-frequency = <0>; + interrupts = <3>; + interrupt-parent = <&PIC>; + }; + + serial1: serial@12100 { + compatible = "ns16550"; + reg = <0x12100 0x20>; + reg-shift = <2>; + clock-frequency = <0>; + interrupts = <4>; + interrupt-parent = <&PIC>; + }; + + usb@50000 { + compatible = "mrvl,usb-ehci", "usb-ehci"; + reg = <0x50000 0x1000>; + interrupts = <17 16>; + interrupt-parent = <&PIC>; + }; + + idma@60000 { + compatible = "mrvl,idma"; + reg = <0x60000 0x1000>; + interrupts = <24 25 26 27 23>; + interrupt-parent = <&PIC>; + }; + + sata@80000 { + compatible = "mrvl,sata"; + reg = <0x80000 0x6000>; + interrupts = <29>; + interrupt-parent = <&PIC>; + }; + }; +}; Added: head/sys/boot/fdt/dts/db88f5281.dts ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/db88f5281.dts Wed May 26 09:50:09 2010 (r208561) @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2010 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Semihalf under sponsorship from + * the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Marvell DB-88F5281 Device Tree Source. + * + * $FreeBSD$ + */ + +/dts-v1/; + +/ { + model = "mrvl,DB-88F5281"; + compatible = "DB-88F5281-BP", "DB-88F5281-BP-A"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + serial0 = &serial0; + serial1 = &serial1; + mpp = &MPP; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "ARM,88FR531"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; // 128M at 0x0 + }; + + localbus@f1000000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "mrvl,lbc"; + + /* This reflects CPU decode windows setup. */ + ranges = <0x0 0x0f 0xf9300000 0x00100000 + 0x1 0x1e 0xfa000000 0x00100000 + 0x2 0x1d 0xfa100000 0x02000000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x00100000>; + bank-width = <2>; + device-width = <1>; + }; + + led@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "led"; + reg = <0x1 0x0 0x00100000>; + }; + + nor@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x2 0x0 0x02000000>; + bank-width = <2>; + device-width = <1>; + }; + }; + + soc88f5281@f1000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0xf1000000 0x00100000>; + bus-frequency = <0>; + + PIC: pic@20200 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x20200 0x3c>; + compatible = "mrvl,pic"; + }; + + timer@20300 { + compatible = "mrvl,timer"; + reg = <0x20300 0x30>; + interrupts = <0>; + interrupt-parent = <&PIC>; + mrvl,has-wdt; + }; + + MPP: mpp@10000 { + #pin-cells = <2>; + compatible = "mrvl,mpp"; + reg = <0x10000 0x54>; + pin-count = <20>; + pin-map = < + 0 3 /* MPP[0]: GPIO[0] */ + 2 2 /* MPP[2]: PCI_REQn[3] */ + 3 2 /* MPP[3]: PCI_GNTn[3] */ + 4 2 /* MPP[4]: PCI_REQn[4] */ + 5 2 /* MPP[5]: PCI_GNTn[4] */ + 6 3 /* MPP[6]: <UNKNOWN> */ + 7 3 /* MPP[7]: <UNKNOWN> */ + 8 3 /* MPP[8]: <UNKNOWN> */ + 9 3 /* MPP[9]: <UNKNOWN> */ + 14 4 /* MPP[14]: NAND Flash REn[2] */ + 15 4 /* MPP[15]: NAND Flash WEn[2] */ + 16 0 /* MPP[16]: UA1_RXD */ + 17 0 /* MPP[17]: UA1_TXD */ + 18 0 /* MPP[18]: UA1_CTS */ + 19 0 >; /* MPP[19]: UA1_RTS */ + }; + + GPIO: gpio@10100 { + #gpio-cells = <3>; + compatible = "mrvl,gpio"; + reg = <0x10100 0x20>; + gpio-controller; + interrupts = <6 7 8 9>; + interrupt-parent = <&PIC>; + }; + + twsi@11000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mrvl,twsi"; + reg = <0x11000 0x20>; + interrupts = <43>; + interrupt-parent = <&PIC>; + }; + + enet0: ethernet@72000 { + #address-cells = <1>; + #size-cells = <1>; + model = "V1"; + compatible = "mrvl,ge"; + reg = <0x72000 0x2000>; + ranges = <0x0 0x72000 0x2000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <18 19 20 21 22>; + interrupt-parent = <&PIC>; + phy-handle = <&phy0>; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mrvl,mdio"; + + phy0: ethernet-phy@0 { + reg = <0x8>; + }; + }; + }; + + serial0: serial@12000 { + compatible = "ns16550"; + reg = <0x12000 0x20>; + reg-shift = <2>; + clock-frequency = <0>; + interrupts = <3>; + interrupt-parent = <&PIC>; + }; + + serial1: serial@12100 { + compatible = "ns16550"; + reg = <0x12100 0x20>; + reg-shift = <2>; + clock-frequency = <0>; + interrupts = <4>; + interrupt-parent = <&PIC>; + }; + + usb@50000 { + compatible = "mrvl,usb-ehci", "usb-ehci"; + reg = <0x50000 0x1000>; + interrupts = <17 16>; + interrupt-parent = <&PIC>; + }; + + idma@60000 { + compatible = "mrvl,idma"; + reg = <0x60000 0x1000>; + interrupts = <24 25 26 27 23>; + interrupt-parent = <&PIC>; + }; + }; +}; Added: head/sys/boot/fdt/dts/db88f6281.dts ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/db88f6281.dts Wed May 26 09:50:09 2010 (r208561) @@ -0,0 +1,306 @@ +/* + * Copyright (c) 2009-2010 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Semihalf under sponsorship from + * the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Marvell DB-88F6281 Device Tree Source. + * + * $FreeBSD$ + */ + +/dts-v1/; + +/ { + model = "mrvl,DB-88F6281"; + compatible = "DB-88F6281-BP", "DB-88F6281-BP-A"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + mpp = &MPP; + pci0 = &pci0; + serial0 = &serial0; + serial1 = &serial1; + soc = &SOC; + sram = &SRAM; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "ARM,88FR131"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x4000>; // L1, 16K + i-cache-size = <0x4000>; // L1, 16K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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