Date: Sun, 16 Nov 2003 04:53:06 -0800 From: Luigi Rizzo <rizzo@icir.org> To: Jeff Roberson <jroberson@chesapeake.net> Cc: cvs-src@FreeBSD.org Subject: Re: cvs commit: src/sys/netinet in_var.h ip_fastfwd.c ip_flow.c ip_flow.h ip_input.c ip_output.c src/sys/sys mbuf.h src/sys/conf files src/sys/net if_arcsubr.c if_ef.c if_ethersubr.c if_fddisubr.c if_ Message-ID: <20031116045306.A66798@xorpc.icir.org> In-Reply-To: <20031116071813.S10222-100000@mail.chesapeake.net>; from jroberson@chesapeake.net on Sun, Nov 16, 2003 at 07:19:53AM -0500 References: <20031116003939.A10853@xorpc.icir.org> <20031116071813.S10222-100000@mail.chesapeake.net>
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On Sun, Nov 16, 2003 at 07:19:53AM -0500, Jeff Roberson wrote: ... > > might result in the second timing call being executed before > > the section of code in the middle is complete. There is > > some nonintuitive instruction (which i now forget) to flush the > > execution pipeline which can be used around the section of > > code you want to time. > > Reading the tsc is also a serializing instruction. I often use it to > accurately measure things that take as few as 20 cycles no, according to the intel documentation it is not, and i myself have seen bogus results which clearly indicate that it is not. There was a thread on the freebsd mailing lists a few months ago. cheers luigi
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