Date: Thu, 21 Jan 2010 02:21:31 +0000 (UTC) From: Neel Natu <neel@FreeBSD.org> To: cvs-src-old@freebsd.org Subject: cvs commit: src/sys/mips/mips exception.S Message-ID: <201001210221.o0L2LjqF062068@repoman.freebsd.org>
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neel 2010-01-21 02:21:31 UTC
FreeBSD src repository
Modified files:
sys/mips/mips exception.S
Log:
SVN rev 202732 on 2010-01-21 02:21:31Z by neel
Get rid of redundant setting of interrupt enable bit when restoring the status
register from the PCB.
Remove a couple of misleading comments while I am here. The comments are
misleading because they imply that interrupts will be enabled after the
status register is restored from the PCB. This is not the case because
the processor is at the exception level (SR_EXL is set).
Approved by: imp (mentor)
Revision Changes Path
1.4 +1 -13 src/sys/mips/mips/exception.S
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