Date: Sat, 22 Mar 1997 10:55:01 -0800 (PST) From: KATO Takenori <kato> To: CVS-committers, cvs-all, cvs-sys Subject: cvs commit: src/sys/pc98/i386 machdep.c trap.c locore.s src/sys/i386/conf files.i386 options.i386 src/sys/i386/i386 identcpu.c locore.s machdep.c src/sys/i386/include cpufunc.h cputypes.h md_var.h specialreg.h src/sys/i386/isa/bs bshw_dma.c bsif.h src/sys/pc98/conf Makefile.pc98 files.pc98 options.pc98 src/sys/pc98/pc98 pc98.c Message-ID: <199703221855.KAA24306@freefall.freebsd.org>
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kato 97/03/22 10:54:59
Modified: sys/i386/conf files.i386 options.i386
sys/i386/i386 identcpu.c locore.s machdep.c
sys/i386/include cpufunc.h cputypes.h md_var.h specialreg.h
sys/i386/isa/bs bshw_dma.c bsif.h
sys/pc98/conf Makefile.pc98 files.pc98 options.pc98
sys/pc98/i386 machdep.c trap.c
sys/pc98/pc98 pc98.c
Removed: sys/pc98/i386 locore.s
Log:
Improved CPU identification and initialization routines. This
supports All Cyrix CPUs, IBM Blue Lightning CPU and NexGen (now AMD)
Nx586 CPU, and initialize special registers of Cyrix CPU and msr of
IBM Blue Lightning CPU.
If revision of Cyrix 6x86 CPU < 2.7, CPU cache is enabled in
write-through mode. This can be disabled by kernel configuration
options.
Reviewed by: Bruce Evans <bde@freebsd.org> and
Jordan K. Hubbard <jkh@freebsd.org>
Revision Changes Path
1.157 +2 -1 src/sys/i386/conf/files.i386
1.38 +18 -5 src/sys/i386/conf/options.i386
1.14 +290 -7 src/sys/i386/i386/identcpu.c
1.82 +92 -81 src/sys/i386/i386/locore.s
1.230 +11 -3 src/sys/i386/i386/machdep.c
1.62 +15 -1 src/sys/i386/include/cpufunc.h
1.8 +6 -2 src/sys/i386/include/cputypes.h
1.13 +7 -1 src/sys/i386/include/md_var.h
1.13 +172 -44 src/sys/i386/include/specialreg.h
1.4 +4 -6 src/sys/i386/isa/bs/bshw_dma.c
1.3 +1 -0 src/sys/i386/isa/bs/bsif.h
1.12 +4 -4 src/sys/pc98/conf/Makefile.pc98
1.18 +2 -1 src/sys/pc98/conf/files.pc98
1.19 +16 -5 src/sys/pc98/conf/options.pc98
1.30 +16 -4 src/sys/pc98/i386/machdep.c
1.14 +11 -11 src/sys/pc98/i386/trap.c
1.19 +7 -7 src/sys/pc98/pc98/pc98.c
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