Date: Sun, 25 Jun 2006 08:26:34 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 99974 for review Message-ID: <200606250826.k5P8QYEt084971@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=99974 Change 99974 by imp@imp_lighthouse on 2006/06/25 08:26:29 Checkpoint work in progress to make units != 0 work. they aren't initialized as a console, so don't presently work. We also shouldn't be turning on interrupt bits in the console code since it is polled. Affected files ... .. //depot/projects/arm/src/sys/arm/at91/uart_dev_at91usart.c#24 edit Differences ... ==== //depot/projects/arm/src/sys/arm/at91/uart_dev_at91usart.c#24 (text+ko) ==== @@ -72,6 +72,9 @@ } \ } while (0); +#define BAUD2DIVISOR(b) \ + ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10) + /* * Low-level UART interface. */ @@ -167,6 +170,13 @@ mr &= ~USART_MR_MSBF; /* lsb first */ mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */ + WR4(bas, USART_MR, mr); + + /* + * Set the baud rate + */ + WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate)); + /* XXX Need to take possible synchronous mode into account */ return (0); } @@ -202,9 +212,11 @@ cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX; WR4(bas, USART_CR, cr); WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); +#if 0 WR4(bas, USART_IER, USART_CSR_TIMEOUT | USART_CSR_TXRDY | USART_CSR_RXRDY | USART_CSR_RXBRK | USART_CSR_ENDRX | USART_CSR_ENDTX); +#endif /* Set the receive timeout to be 1.5 character times. */ WR4(bas, USART_RTOR, 12); } @@ -295,6 +307,7 @@ at91_usart_bus_attach(struct uart_softc *sc) { int err; + uint32_t cr; struct at91_usart_softc *atsc; atsc = (struct at91_usart_softc *)sc; @@ -317,6 +330,17 @@ err = bus_dmamap_create(atsc->dmatag, 0, &atsc->rx_map); if (err != 0) goto errout; + + /* Turn on rx and tx */ + cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX; + WR4(&sc->sc_bas, USART_CR, cr); + WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); + WR4(&sc->sc_bas, USART_IDR, 0xffffffff); + WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT | + USART_CSR_TXRDY | USART_CSR_RXRDY | + USART_CSR_RXBRK | USART_CSR_ENDRX | USART_CSR_ENDTX); + /* Set the receive timeout to be 1.5 character times. */ + WR4(&sc->sc_bas, USART_RTOR, 12); errout:; // XXX bad return (err); @@ -360,6 +384,8 @@ WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz); WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN); uart_unlock(sc->sc_hwmtx); + if (device_get_unit(sc->sc_dev)) + device_printf(sc->sc_dev, "transmit %d bytes\n", sc->sc_txdatasz); #else for (int i = 0; i < sc->sc_txdatasz; i++) at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]); @@ -425,6 +451,8 @@ int ipend = 0; struct at91_usart_softc *atsc; + if (device_get_unit(sc->sc_dev)) + device_printf(sc->sc_dev, "ipend csr %#x\n", csr); atsc = (struct at91_usart_softc *)sc; if (csr & USART_CSR_ENDTX) { bus_dmamap_sync(atsc->dmatag, atsc->tx_map, @@ -479,6 +507,15 @@ static int at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) { + switch (request) { + case UART_IOCTL_BREAK: + case UART_IOCTL_IFLOW: + case UART_IOCTL_OFLOW: + break; + case UART_IOCTL_BAUD: + WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data)); + return (0); + } return (EINVAL); } struct uart_class at91_usart_class = {
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