Date: Tue, 12 Apr 2016 12:55:50 +0000 From: =?utf-8?Q?Maria=20Shumusti?= <maria@fashionablyin.com> To: <svn-src-head@freebsd.org> Subject: =?utf-8?Q?Re=3A=C2=A0Fashionablyin=20New=20York?= Message-ID: <8e7d8ec661c4606682b4765ddf2b96bde3b.20160412125514@mail22.atl11.rsgsv.net>
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You subscribed on our website - Fashionablyin.com Our mailing address is: FASHIONABLYIN 2-4 Unit 27 Exmoor Street London=2C W10 6BD United Kingdom Want to change how you receive these emails? You can ** update your preferences (http://fashionablyin.us1.list-manage.c= om/profile?u=3D8e7d8ec661c4606682b4765dd&id=3Db4c7b5ed13&e=3Df2b96bde3b) or ** unsubscribe from this list (http://fashionablyin.us1.list-manage.com= /unsubscribe?u=3D8e7d8ec661c4606682b4765dd&id=3Db4c7b5ed13&e=3Df2b96bde3b&c= =3D814f1f60ac) From owner-svn-src-head@freebsd.org Tue Apr 12 13:30:41 2016 Return-Path: <owner-svn-src-head@freebsd.org> Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 53E1BB0D3BB; Tue, 12 Apr 2016 13:30:41 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 178DA1934; Tue, 12 Apr 2016 13:30:41 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u3CDUeLQ098620; Tue, 12 Apr 2016 13:30:40 GMT (envelope-from avg@FreeBSD.org) Received: (from avg@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u3CDUdrB098615; Tue, 12 Apr 2016 13:30:39 GMT (envelope-from avg@FreeBSD.org) Message-Id: <201604121330.u3CDUdrB098615@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: avg set sender to avg@FreeBSD.org using -f From: Andriy Gapon <avg@FreeBSD.org> Date: Tue, 12 Apr 2016 13:30:39 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r297857 - in head/sys: amd64/amd64 i386/i386 x86/include x86/x86 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: SVN commit messages for the src tree for head/-current <svn-src-head.freebsd.org> List-Unsubscribe: <https://lists.freebsd.org/mailman/options/svn-src-head>, <mailto:svn-src-head-request@freebsd.org?subject=unsubscribe> List-Archive: <http://lists.freebsd.org/pipermail/svn-src-head/>; List-Post: <mailto:svn-src-head@freebsd.org> List-Help: <mailto:svn-src-head-request@freebsd.org?subject=help> List-Subscribe: <https://lists.freebsd.org/mailman/listinfo/svn-src-head>, <mailto:svn-src-head-request@freebsd.org?subject=subscribe> X-List-Received-Date: Tue, 12 Apr 2016 13:30:41 -0000 Author: avg Date: Tue Apr 12 13:30:39 2016 New Revision: 297857 URL: https://svnweb.freebsd.org/changeset/base/297857 Log: re-enable AMD Topology extension on certain models if disabled by BIOS Some BIOSes disable AMD Topology extension on AMD Family 15h notebook processors. We re-enable the extension, so that we can properly discover core and cache topology. Linux seems to do the same. Reported by: Johannes Dieterich <dieterich.joh@gmail.com> Reviewed by: jhb, kib Tested by: Johannes Dieterich <dieterich.joh@gmail.com> (earlier version) MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D5883 Modified: head/sys/amd64/amd64/mp_machdep.c head/sys/i386/i386/mp_machdep.c head/sys/x86/include/specialreg.h head/sys/x86/include/x86_var.h head/sys/x86/x86/identcpu.c Modified: head/sys/amd64/amd64/mp_machdep.c ============================================================================== --- head/sys/amd64/amd64/mp_machdep.c Tue Apr 12 12:31:41 2016 (r297856) +++ head/sys/amd64/amd64/mp_machdep.c Tue Apr 12 13:30:39 2016 (r297857) @@ -247,7 +247,7 @@ init_secondary(void) wrmsr(MSR_FSBASE, 0); /* User value */ wrmsr(MSR_GSBASE, (u_int64_t)pc); wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */ - intel_fix_cpuid(); + fix_cpuid(); lidt(&r_idt); Modified: head/sys/i386/i386/mp_machdep.c ============================================================================== --- head/sys/i386/i386/mp_machdep.c Tue Apr 12 12:31:41 2016 (r297856) +++ head/sys/i386/i386/mp_machdep.c Tue Apr 12 13:30:39 2016 (r297857) @@ -242,7 +242,7 @@ init_secondary(void) pc->pc_prvspace = pc; pc->pc_curthread = 0; - intel_fix_cpuid(); + fix_cpuid(); gdt_segs[GPRIV_SEL].ssd_base = (int) pc; gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss; Modified: head/sys/x86/include/specialreg.h ============================================================================== --- head/sys/x86/include/specialreg.h Tue Apr 12 12:31:41 2016 (r297856) +++ head/sys/x86/include/specialreg.h Tue Apr 12 13:30:39 2016 (r297857) @@ -816,6 +816,7 @@ #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ +#define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */ #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ #define MSR_MC0_CTL_MASK 0xc0010044 Modified: head/sys/x86/include/x86_var.h ============================================================================== --- head/sys/x86/include/x86_var.h Tue Apr 12 12:31:41 2016 (r297856) +++ head/sys/x86/include/x86_var.h Tue Apr 12 13:30:39 2016 (r297857) @@ -103,7 +103,7 @@ void dump_drop_page(vm_paddr_t); void identify_cpu(void); void initializecpu(void); void initializecpucache(void); -bool intel_fix_cpuid(void); +bool fix_cpuid(void); void fillw(int /*u_short*/ pat, void *base, size_t cnt); int is_physical_memory(vm_paddr_t addr); int isa_nmi(int cd); Modified: head/sys/x86/x86/identcpu.c ============================================================================== --- head/sys/x86/x86/identcpu.c Tue Apr 12 12:31:41 2016 (r297856) +++ head/sys/x86/x86/identcpu.c Tue Apr 12 13:30:39 2016 (r297857) @@ -1342,23 +1342,22 @@ identify_hypervisor(void) } } -/* - * Clear "Limit CPUID Maxval" bit and return true if the caller should - * get the largest standard CPUID function number again if it is set - * from BIOS. It is necessary for probing correct CPU topology later - * and for the correct operation of the AVX-aware userspace. - */ bool -intel_fix_cpuid(void) +fix_cpuid(void) { uint64_t msr; - if (cpu_vendor_id != CPU_VENDOR_INTEL) - return (false); - if ((CPUID_TO_FAMILY(cpu_id) == 0xf && + /* + * Clear "Limit CPUID Maxval" bit and return true if the caller should + * get the largest standard CPUID function number again if it is set + * from BIOS. It is necessary for probing correct CPU topology later + * and for the correct operation of the AVX-aware userspace. + */ + if (cpu_vendor_id == CPU_VENDOR_INTEL && + ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) || (CPUID_TO_FAMILY(cpu_id) == 0x6 && - CPUID_TO_MODEL(cpu_id) >= 0xe)) { + CPUID_TO_MODEL(cpu_id) >= 0xe))) { msr = rdmsr(MSR_IA32_MISC_ENABLE); if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { msr &= ~IA32_MISC_EN_LIMCPUID; @@ -1366,6 +1365,22 @@ intel_fix_cpuid(void) return (true); } } + + /* + * Re-enable AMD Topology Extension that could be disabled by BIOS + * on some notebook processors. Without the extension it's really + * hard to determine the correct CPU cache topology. + * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h + * Models 60h-6Fh Processors, Publication # 50742. + */ + if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x15) { + msr = rdmsr(MSR_EXTFEATURES); + if ((msr & ((uint64_t)1 << 54)) == 0) { + msr |= (uint64_t)1 << 54; + wrmsr(MSR_EXTFEATURES, msr); + return (true); + } + } return (false); } @@ -1403,7 +1418,7 @@ identify_cpu(void) identify_hypervisor(); cpu_vendor_id = find_cpu_vendor_id(); - if (intel_fix_cpuid()) { + if (fix_cpuid()) { do_cpuid(0, regs); cpu_high = regs[0]; }
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