Date: Wed, 24 Feb 2016 22:07:56 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r296011 - in projects/clang380-import: contrib/llvm/lib/CodeGen contrib/llvm/lib/Target/AArch64 contrib/llvm/lib/Target/PowerPC contrib/llvm/lib/Target/X86 contrib/llvm/tools/clang/lib/... Message-ID: <201602242207.u1OM7uJB075837@repo.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: dim Date: Wed Feb 24 22:07:56 2016 New Revision: 296011 URL: https://svnweb.freebsd.org/changeset/base/296011 Log: Update llvm and clang to release_38 branch r261684. Modified: projects/clang380-import/contrib/llvm/lib/CodeGen/RegAllocFast.cpp projects/clang380-import/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp projects/clang380-import/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.h projects/clang380-import/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp projects/clang380-import/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.h projects/clang380-import/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp projects/clang380-import/contrib/llvm/lib/Target/X86/X86ISelLowering.h projects/clang380-import/contrib/llvm/lib/Target/X86/X86InstrCompiler.td projects/clang380-import/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp projects/clang380-import/contrib/llvm/tools/clang/lib/Sema/SemaExpr.cpp projects/clang380-import/lib/clang/include/clang/Basic/Version.inc Directory Properties: projects/clang380-import/contrib/llvm/ (props changed) projects/clang380-import/contrib/llvm/tools/clang/ (props changed) Modified: projects/clang380-import/contrib/llvm/lib/CodeGen/RegAllocFast.cpp ============================================================================== --- projects/clang380-import/contrib/llvm/lib/CodeGen/RegAllocFast.cpp Wed Feb 24 22:01:45 2016 (r296010) +++ projects/clang380-import/contrib/llvm/lib/CodeGen/RegAllocFast.cpp Wed Feb 24 22:07:56 2016 (r296011) @@ -1002,11 +1002,13 @@ void RAFast::AllocateBasicBlock() { unsigned DefOpEnd = MI->getNumOperands(); if (MI->isCall()) { - // Spill all virtregs before a call. This serves two purposes: 1. If an + // Spill all virtregs before a call. This serves one purpose: If an // exception is thrown, the landing pad is going to expect to find - // registers in their spill slots, and 2. we don't have to wade through - // all the <imp-def> operands on the call instruction. - DefOpEnd = VirtOpEnd; + // registers in their spill slots. + // Note: although this is appealing to just consider all definitions + // as call-clobbered, this is not correct because some of those + // definitions may be used later on and we do not want to reuse + // those for virtual registers in between. DEBUG(dbgs() << " Spilling remaining registers before call.\n"); spillAll(MI); Modified: projects/clang380-import/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp ============================================================================== --- projects/clang380-import/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp Wed Feb 24 22:01:45 2016 (r296010) +++ projects/clang380-import/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp Wed Feb 24 22:07:56 2016 (r296011) @@ -275,6 +275,18 @@ static bool isCSSave(MachineInstr *MBBI) MBBI->getOpcode() == AArch64::STPDpre; } +bool AArch64FrameLowering::canUseAsPrologue( + const MachineBasicBlock &MBB) const { + const MachineFunction *MF = MBB.getParent(); + const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>(); + const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); + + // Don't need a scratch register if we're not going to re-align the stack. + // Otherwise, we may need a scratch register to be available and we do not + // support that for now. + return !RegInfo->needsStackRealignment(*MF); +} + void AArch64FrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = MBB.begin(); Modified: projects/clang380-import/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.h ============================================================================== --- projects/clang380-import/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.h Wed Feb 24 22:01:45 2016 (r296010) +++ projects/clang380-import/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.h Wed Feb 24 22:07:56 2016 (r296011) @@ -37,6 +37,8 @@ public: void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; + bool canUseAsPrologue(const MachineBasicBlock &MBB) const override; + int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override; int resolveFrameIndexReference(const MachineFunction &MF, int FI, Modified: projects/clang380-import/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp ============================================================================== --- projects/clang380-import/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp Wed Feb 24 22:01:45 2016 (r296010) +++ projects/clang380-import/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp Wed Feb 24 22:07:56 2016 (r296011) @@ -556,16 +556,42 @@ void PPCFrameLowering::replaceFPWithReal } } -bool PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, - bool UseAtEnd, - unsigned *ScratchRegister) const { +/* This function will do the following: + - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12 + respectively (defaults recommended by the ABI) and return true + - If MBB is not an entry block, initialize the register scavenger and look + for available registers. + - If the defaults (R0/R12) are available, return true + - If TwoUniqueRegsRequired is set to true, it looks for two unique + registers. Otherwise, look for a single available register. + - If the required registers are found, set SR1 and SR2 and return true. + - If the required registers are not found, set SR2 or both SR1 and SR2 to + PPC::NoRegister and return false. + + Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired + is not set, this function will attempt to find two different registers, but + still return true if only one register is available (and set SR1 == SR2). +*/ +bool +PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, + bool UseAtEnd, + bool TwoUniqueRegsRequired, + unsigned *SR1, + unsigned *SR2) const { RegScavenger RS; - unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0; + unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0; + unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; + + // Set the defaults for the two scratch registers. + if (SR1) + *SR1 = R0; - if (ScratchRegister) - *ScratchRegister = R0; + if (SR2) { + assert (SR1 && "Asking for the second scratch register but not the first?"); + *SR2 = R12; + } - // If MBB is an entry or exit block, use R0 as the scratch register + // If MBB is an entry or exit block, use R0 and R12 as the scratch registers. if ((UseAtEnd && MBB->isReturnBlock()) || (!UseAtEnd && (&MBB->getParent()->front() == MBB))) return true; @@ -573,8 +599,8 @@ bool PPCFrameLowering::findScratchRegist RS.enterBasicBlock(MBB); if (UseAtEnd && !MBB->empty()) { - // The scratch register will be used at the end of the block, so must consider - // all registers used within the block + // The scratch register will be used at the end of the block, so must + // consider all registers used within the block MachineBasicBlock::iterator MBBI = MBB->getFirstTerminator(); // If no terminator, back iterator up to previous instruction. @@ -584,35 +610,86 @@ bool PPCFrameLowering::findScratchRegist if (MBBI != MBB->begin()) RS.forward(MBBI); } - - if (!RS.isRegUsed(R0)) + + // If the two registers are available, we're all good. + // Note that we only return here if both R0 and R12 are available because + // although the function may not require two unique registers, it may benefit + // from having two so we should try to provide them. + if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12)) return true; - unsigned Reg = RS.FindUnusedReg(Subtarget.isPPC64() ? &PPC::G8RCRegClass - : &PPC::GPRCRegClass); - - // Make sure the register scavenger was able to find an available register - // If not, use R0 but return false to indicate no register was available and - // R0 must be used (as recommended by the ABI) - if (Reg == 0) - return false; + // Get the list of callee-saved registers for the target. + const PPCRegisterInfo *RegInfo = + static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); + const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); - if (ScratchRegister) - *ScratchRegister = Reg; + // Get all the available registers in the block. + BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass : + &PPC::GPRCRegClass); + + // We shouldn't use callee-saved registers as scratch registers as they may be + // available when looking for a candidate block for shrink wrapping but not + // available when the actual prologue/epilogue is being emitted because they + // were added as live-in to the prologue block by PrologueEpilogueInserter. + for (int i = 0; CSRegs[i]; ++i) + BV.reset(CSRegs[i]); + + // Set the first scratch register to the first available one. + if (SR1) { + int FirstScratchReg = BV.find_first(); + *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg; + } + + // If there is another one available, set the second scratch register to that. + // Otherwise, set it to either PPC::NoRegister if this function requires two + // or to whatever SR1 is set to if this function doesn't require two. + if (SR2) { + int SecondScratchReg = BV.find_next(*SR1); + if (SecondScratchReg != -1) + *SR2 = SecondScratchReg; + else + *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1; + } + + // Now that we've done our best to provide both registers, double check + // whether we were unable to provide enough. + if (BV.count() < (TwoUniqueRegsRequired ? 2 : 1)) + return false; return true; } +// We need a scratch register for spilling LR and for spilling CR. By default, +// we use two scratch registers to hide latency. However, if only one scratch +// register is available, we can adjust for that by not overlapping the spill +// code. However, if we need to realign the stack (i.e. have a base pointer) +// and the stack frame is large, we need two scratch registers. +bool +PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const { + const PPCRegisterInfo *RegInfo = + static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); + MachineFunction &MF = *(MBB->getParent()); + bool HasBP = RegInfo->hasBasePointer(MF); + unsigned FrameSize = determineFrameLayout(MF, false); + int NegFrameSize = -FrameSize; + bool IsLargeFrame = !isInt<16>(NegFrameSize); + MachineFrameInfo *MFI = MF.getFrameInfo(); + unsigned MaxAlign = MFI->getMaxAlignment(); + + return IsLargeFrame && HasBP && MaxAlign > 1; +} + bool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); - return findScratchRegister(TmpMBB, false, nullptr); + return findScratchRegister(TmpMBB, false, + twoUniqueScratchRegsRequired(TmpMBB)); } bool PPCFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); - return findScratchRegister(TmpMBB, true, nullptr); + return findScratchRegister(TmpMBB, true); } void PPCFrameLowering::emitPrologue(MachineFunction &MF, @@ -664,6 +741,7 @@ void PPCFrameLowering::emitPrologue(Mach PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); bool MustSaveLR = FI->mustSaveLR(); const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); + bool MustSaveCR = !MustSaveCRs.empty(); // Do we have a frame pointer and/or base pointer for this function? bool HasFP = hasFP(MF); bool HasBP = RegInfo->hasBasePointer(MF); @@ -701,9 +779,15 @@ void PPCFrameLowering::emitPrologue(Mach assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."); - findScratchRegister(&MBB, false, &ScratchReg); - assert(ScratchReg && "No scratch register!"); - + // Using the same bool variable as below to supress compiler warnings. + bool SingleScratchReg = + findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB), + &ScratchReg, &TempReg); + assert(SingleScratchReg && + "Required number of registers not available in this block"); + + SingleScratchReg = ScratchReg == TempReg; + int LROffset = getReturnSaveOffset(); int FPOffset = 0; @@ -748,13 +832,30 @@ void PPCFrameLowering::emitPrologue(Mach // indexed into with a simple STDU/STWU/STD/STW immediate offset operand. bool isLargeFrame = !isInt<16>(NegFrameSize); + assert((isPPC64 || !MustSaveCR) && + "Prologue CR saving supported only in 64-bit mode"); + + // If we need to spill the CR and the LR but we don't have two separate + // registers available, we must spill them one at a time + if (MustSaveCR && SingleScratchReg && MustSaveLR) { + // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. + // If only one or two CR fields are clobbered, it could be more + // efficient to use mfocrf to selectively save just those fields. + MachineInstrBuilder MIB = + BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); + for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) + MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); + BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) + .addReg(TempReg, getKillRegState(true)) + .addImm(8) + .addReg(SPReg); + } + if (MustSaveLR) BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); - assert((isPPC64 || MustSaveCRs.empty()) && - "Prologue CR saving supported only in 64-bit mode"); - - if (!MustSaveCRs.empty()) { // will only occur for PPC64 + if (MustSaveCR && + !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. // If only one or two CR fields are clobbered, it could be more // efficient to use mfocrf to selectively save just those fields. @@ -792,7 +893,8 @@ void PPCFrameLowering::emitPrologue(Mach .addImm(LROffset) .addReg(SPReg); - if (!MustSaveCRs.empty()) // will only occur for PPC64 + if (MustSaveCR && + !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) .addReg(TempReg, getKillRegState(true)) .addImm(8) @@ -811,6 +913,7 @@ void PPCFrameLowering::emitPrologue(Mach .addReg(SPReg); } + // This condition must be kept in sync with canUseAsPrologue. if (HasBP && MaxAlign > 1) { if (isPPC64) BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) @@ -828,6 +931,7 @@ void PPCFrameLowering::emitPrologue(Mach .addReg(ScratchReg, RegState::Kill) .addImm(NegFrameSize); } else { + assert(!SingleScratchReg && "Only a single scratch reg available"); BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg) .addImm(NegFrameSize >> 16); BuildMI(MBB, MBBI, dl, OrImmInst, TempReg) @@ -951,7 +1055,7 @@ void PPCFrameLowering::emitPrologue(Mach // For SVR4, don't emit a move for the CR spill slot if we haven't // spilled CRs. if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) - && MustSaveCRs.empty()) + && !MustSaveCR) continue; // For 64-bit SVR4 when we have spilled CRs, the spill location @@ -1005,6 +1109,7 @@ void PPCFrameLowering::emitEpilogue(Mach PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); bool MustSaveLR = FI->mustSaveLR(); const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); + bool MustSaveCR = !MustSaveCRs.empty(); // Do we have a frame pointer and/or base pointer for this function? bool HasFP = hasFP(MF); bool HasBP = RegInfo->hasBasePointer(MF); @@ -1026,14 +1131,19 @@ void PPCFrameLowering::emitEpilogue(Mach : PPC::ADDI ); const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 : PPC::ADD4 ); - + int LROffset = getReturnSaveOffset(); int FPOffset = 0; - findScratchRegister(&MBB, true, &ScratchReg); - assert(ScratchReg && "No scratch register!"); - + // Using the same bool variable as below to supress compiler warnings. + bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg, + &TempReg); + assert(SingleScratchReg && + "Could not find an available scratch register"); + + SingleScratchReg = ScratchReg == TempReg; + if (HasFP) { if (isSVR4ABI) { MachineFrameInfo *FFI = MF.getFrameInfo(); @@ -1130,15 +1240,27 @@ void PPCFrameLowering::emitEpilogue(Mach } } + assert((isPPC64 || !MustSaveCR) && + "Epilogue CR restoring supported only in 64-bit mode"); + + // If we need to save both the LR and the CR and we only have one available + // scratch register, we must do them one at a time. + if (MustSaveCR && SingleScratchReg && MustSaveLR) { + BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) + .addImm(8) + .addReg(SPReg); + for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) + BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) + .addReg(TempReg, getKillRegState(i == e-1)); + } + if (MustSaveLR) BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) .addImm(LROffset) .addReg(SPReg); - assert((isPPC64 || MustSaveCRs.empty()) && - "Epilogue CR restoring supported only in 64-bit mode"); - - if (!MustSaveCRs.empty()) // will only occur for PPC64 + if (MustSaveCR && + !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) .addImm(8) .addReg(SPReg); @@ -1160,7 +1282,8 @@ void PPCFrameLowering::emitEpilogue(Mach .addImm(BPOffset) .addReg(SPReg); - if (!MustSaveCRs.empty()) // will only occur for PPC64 + if (MustSaveCR && + !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) .addReg(TempReg, getKillRegState(i == e-1)); Modified: projects/clang380-import/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.h ============================================================================== --- projects/clang380-import/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.h Wed Feb 24 22:01:45 2016 (r296010) +++ projects/clang380-import/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.h Wed Feb 24 22:07:56 2016 (r296011) @@ -30,28 +30,41 @@ class PPCFrameLowering: public TargetFra const unsigned BasePointerSaveOffset; /** - * \brief Find a register that can be used in function prologue and epilogue + * \brief Find register[s] that can be used in function prologue and epilogue * - * Find a register that can be use as the scratch register in function + * Find register[s] that can be use as scratch register[s] in function * prologue and epilogue to save various registers (Link Register, Base - * Pointer, etc.). Prefer R0, if it is available. If it is not available, - * then choose a different register. + * Pointer, etc.). Prefer R0/R12, if available. Otherwise choose whatever + * register[s] are available. * - * This method will return true if an available register was found (including - * R0). If no available registers are found, the method returns false and sets - * ScratchRegister to R0, as per the recommendation in the ABI. + * This method will return true if it is able to find enough unique scratch + * registers (1 or 2 depending on the requirement). If it is unable to find + * enough available registers in the block, it will return false and set + * any passed output parameter that corresponds to a required unique register + * to PPC::NoRegister. * * \param[in] MBB The machine basic block to find an available register for * \param[in] UseAtEnd Specify whether the scratch register will be used at * the end of the basic block (i.e., will the scratch * register kill a register defined in the basic block) - * \param[out] ScratchRegister The scratch register to use - * \return true if a scratch register was found. false of a scratch register - * was not found and R0 is being used as the default. + * \param[in] TwoUniqueRegsRequired Specify whether this basic block will + * require two unique scratch registers. + * \param[out] SR1 The scratch register to use + * \param[out] SR2 The second scratch register. If this pointer is not null + * the function will attempt to set it to an available + * register regardless of whether there is a hard requirement + * for two unique scratch registers. + * \return true if the required number of registers was found. + * false if the required number of scratch register weren't available. + * If either output parameter refers to a required scratch register + * that isn't available, it will be set to an invalid value. */ bool findScratchRegister(MachineBasicBlock *MBB, bool UseAtEnd, - unsigned *ScratchRegister) const; + bool TwoUniqueRegsRequired = false, + unsigned *SR1 = nullptr, + unsigned *SR2 = nullptr) const; + bool twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const; public: PPCFrameLowering(const PPCSubtarget &STI); Modified: projects/clang380-import/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp ============================================================================== --- projects/clang380-import/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 24 22:01:45 2016 (r296010) +++ projects/clang380-import/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 24 22:07:56 2016 (r296011) @@ -22228,6 +22228,35 @@ X86TargetLowering::EmitLoweredCatchPad(M } MachineBasicBlock * +X86TargetLowering::EmitLoweredTLSAddr(MachineInstr *MI, + MachineBasicBlock *BB) const { + // So, here we replace TLSADDR with the sequence: + // adjust_stackdown -> TLSADDR -> adjust_stackup. + // We need this because TLSADDR is lowered into calls + // inside MC, therefore without the two markers shrink-wrapping + // may push the prologue/epilogue pass them. + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); + DebugLoc DL = MI->getDebugLoc(); + MachineFunction &MF = *BB->getParent(); + + // Emit CALLSEQ_START right before the instruction. + unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); + MachineInstrBuilder CallseqStart = + BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0); + BB->insert(MachineBasicBlock::iterator(MI), CallseqStart); + + // Emit CALLSEQ_END right after the instruction. + // We don't call erase from parent because we want to keep the + // original instruction around. + unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); + MachineInstrBuilder CallseqEnd = + BuildMI(MF, DL, TII.get(AdjStackUp)).addImm(0).addImm(0); + BB->insertAfter(MachineBasicBlock::iterator(MI), CallseqEnd); + + return BB; +} + +MachineBasicBlock * X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, MachineBasicBlock *BB) const { // This is pretty easy. We're taking the value that we received from @@ -22607,6 +22636,11 @@ X86TargetLowering::EmitInstrWithCustomIn case X86::TCRETURNri64: case X86::TCRETURNmi64: return BB; + case X86::TLS_addr32: + case X86::TLS_addr64: + case X86::TLS_base_addr32: + case X86::TLS_base_addr64: + return EmitLoweredTLSAddr(MI, BB); case X86::WIN_ALLOCA: return EmitLoweredWinAlloca(MI, BB); case X86::CATCHRET: Modified: projects/clang380-import/contrib/llvm/lib/Target/X86/X86ISelLowering.h ============================================================================== --- projects/clang380-import/contrib/llvm/lib/Target/X86/X86ISelLowering.h Wed Feb 24 22:01:45 2016 (r296010) +++ projects/clang380-import/contrib/llvm/lib/Target/X86/X86ISelLowering.h Wed Feb 24 22:07:56 2016 (r296011) @@ -1129,6 +1129,9 @@ namespace llvm { MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr *MI, + MachineBasicBlock *BB) const; + MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, MachineBasicBlock *BB) const; Modified: projects/clang380-import/contrib/llvm/lib/Target/X86/X86InstrCompiler.td ============================================================================== --- projects/clang380-import/contrib/llvm/lib/Target/X86/X86InstrCompiler.td Wed Feb 24 22:01:45 2016 (r296010) +++ projects/clang380-import/contrib/llvm/lib/Target/X86/X86InstrCompiler.td Wed Feb 24 22:07:56 2016 (r296011) @@ -436,7 +436,7 @@ let Defs = [EAX, ECX, EDX, FP0, FP1, FP2 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], - Uses = [ESP] in { + usesCustomInserter = 1, Uses = [ESP] in { def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), "# TLS_addr32", [(X86tlsaddr tls32addr:$sym)]>, @@ -456,7 +456,7 @@ let Defs = [RAX, RCX, RDX, RSI, RDI, R8, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], - Uses = [RSP] in { + usesCustomInserter = 1, Uses = [RSP] in { def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), "# TLS_addr64", [(X86tlsaddr tls64addr:$sym)]>, Modified: projects/clang380-import/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp ============================================================================== --- projects/clang380-import/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp Wed Feb 24 22:01:45 2016 (r296010) +++ projects/clang380-import/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp Wed Feb 24 22:07:56 2016 (r296011) @@ -3475,6 +3475,7 @@ public: Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList, QualType Ty) const { + const unsigned OverflowLimit = 8; if (const ComplexType *CTy = Ty->getAs<ComplexType>()) { // TODO: Implement this. For now ignore. (void)CTy; @@ -3517,7 +3518,7 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co } llvm::Value *CC = - Builder.CreateICmpULT(NumRegs, Builder.getInt8(8), "cond"); + Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond"); llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs"); llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow"); @@ -3569,6 +3570,8 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co { CGF.EmitBlock(UsingOverflow); + Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr); + // Everything in the overflow area is rounded up to a size of at least 4. CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4); Modified: projects/clang380-import/contrib/llvm/tools/clang/lib/Sema/SemaExpr.cpp ============================================================================== --- projects/clang380-import/contrib/llvm/tools/clang/lib/Sema/SemaExpr.cpp Wed Feb 24 22:01:45 2016 (r296010) +++ projects/clang380-import/contrib/llvm/tools/clang/lib/Sema/SemaExpr.cpp Wed Feb 24 22:07:56 2016 (r296011) @@ -1365,10 +1365,13 @@ Sema::CreateGenericSelectionExpr(SourceL // Decay and strip qualifiers for the controlling expression type, and handle // placeholder type replacement. See committee discussion from WG14 DR423. - ExprResult R = DefaultFunctionArrayLvalueConversion(ControllingExpr); - if (R.isInvalid()) - return ExprError(); - ControllingExpr = R.get(); + { + EnterExpressionEvaluationContext Unevaluated(*this, Sema::Unevaluated); + ExprResult R = DefaultFunctionArrayLvalueConversion(ControllingExpr); + if (R.isInvalid()) + return ExprError(); + ControllingExpr = R.get(); + } // The controlling expression is an unevaluated operand, so side effects are // likely unintended. Modified: projects/clang380-import/lib/clang/include/clang/Basic/Version.inc ============================================================================== --- projects/clang380-import/lib/clang/include/clang/Basic/Version.inc Wed Feb 24 22:01:45 2016 (r296010) +++ projects/clang380-import/lib/clang/include/clang/Basic/Version.inc Wed Feb 24 22:07:56 2016 (r296011) @@ -7,4 +7,4 @@ #define CLANG_VENDOR "FreeBSD " -#define SVN_REVISION "261369" +#define SVN_REVISION "261684"
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201602242207.u1OM7uJB075837>