Date: Wed, 15 May 2013 01:17:59 +0000 (UTC) From: Pyun YongHyeon <yongari@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org Subject: svn commit: r250649 - stable/8/sys/dev/mii Message-ID: <201305150117.r4F1Hxh1084294@svn.freebsd.org>
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Author: yongari Date: Wed May 15 01:17:59 2013 New Revision: 250649 URL: http://svnweb.freebsd.org/changeset/base/250649 Log: MFC r248542: For RTL8211B or later PHYs, enable crossover detection and auto-correction. This change makes re(4) establish a link with a system using non-crossover UTP cable. Modified: stable/8/sys/dev/mii/rgephy.c stable/8/sys/dev/mii/rgephyreg.h Directory Properties: stable/8/sys/ (props changed) stable/8/sys/dev/ (props changed) stable/8/sys/dev/mii/ (props changed) Modified: stable/8/sys/dev/mii/rgephy.c ============================================================================== --- stable/8/sys/dev/mii/rgephy.c Wed May 15 01:16:41 2013 (r250648) +++ stable/8/sys/dev/mii/rgephy.c Wed May 15 01:17:59 2013 (r250649) @@ -517,7 +517,7 @@ static void rgephy_reset(struct mii_softc *sc) { struct rgephy_softc *rsc; - uint16_t ssr; + uint16_t pcr, ssr; rsc = (struct rgephy_softc *)sc; if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && rsc->mii_revision == 3) { @@ -529,6 +529,15 @@ rgephy_reset(struct mii_softc *sc) } } + if (rsc->mii_revision >= 2) { + pcr = PHY_READ(sc, RGEPHY_MII_PCR); + if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { + pcr &= ~RGEPHY_PCR_MDI_MASK; + pcr |= RGEPHY_PCR_MDIX_AUTO; + PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); + } + } + mii_phy_reset(sc); DELAY(1000); rgephy_load_dspcode(sc); Modified: stable/8/sys/dev/mii/rgephyreg.h ============================================================================== --- stable/8/sys/dev/mii/rgephyreg.h Wed May 15 01:16:41 2013 (r250648) +++ stable/8/sys/dev/mii/rgephyreg.h Wed May 15 01:17:59 2013 (r250649) @@ -138,6 +138,17 @@ #define RGEPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ /* RTL8211B(L)/RTL8211C(L) */ +#define RGEPHY_MII_PCR 0x10 /* PHY Specific control register */ +#define RGEPHY_PCR_ASSERT_CRS 0x0800 +#define RGEPHY_PCR_FORCE_LINK 0x0400 +#define RGEPHY_PCR_MDI_MASK 0x0060 +#define RGEPHY_PCR_MDIX_AUTO 0x0040 +#define RGEPHY_PCR_MDIX_MANUAL 0x0020 +#define RGEPHY_PCR_MDI_MANUAL 0x0000 +#define RGEPHY_PCR_CLK125_DIS 0x0010 +#define RGEPHY_PCR_JABBER_DIS 0x0001 + +/* RTL8211B(L)/RTL8211C(L) */ #define RGEPHY_MII_SSR 0x11 /* PHY Specific status register */ #define RGEPHY_SSR_S1000 0x8000 /* 1000Mbps */ #define RGEPHY_SSR_S100 0x4000 /* 100Mbps */
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