Date: Thu, 16 May 1996 04:54:39 -0700 (PDT) From: "Rodney W. Grimes" <rgrimes@GndRsh.aac.dev.com> To: joerg_wunsch@uriah.heep.sax.de Cc: jgreco@brasil.moneng.mei.com, davidg@Root.COM, mmead@Glock.COM, joerg_wunsch@uriah.heep.sax.de, blh@nol.net, hackers@freebsd.org, hardware@freebsd.org Subject: Re: Triton chipset with 256k cache caches 32M only? Message-ID: <199605161154.EAA06145@GndRsh.aac.dev.com> In-Reply-To: <199605161031.MAA01458@uriah.heep.sax.de> from J Wunsch at "May 16, 96 12:31:53 pm"
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> As Rodney W. Grimes wrote: > > > > > ECC has single bit error correction and 2 bit error detection. Better than > > > > parity no matter how you slice it. > > > > Only if you have memory that is failing or you need extreamly reliable > > operation (good memory should have a single bit error rate of something > > like 1 in 10 years). > > I think most of the memory problems we've been observing lately are > not related to the RAM itself, but rather to other hardware problems > (timing, EMC problems). Remember all the reports about ``strange sig > 10/11's'' or the Winbloze ``general protection failure'' mess where > you never know whether it's actually hardware or rather an o/s > failure. Since ECC is not applied to either the Cache SRAM or any of the interconnecting busses it won't help these failures. -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Reliable computers for FreeBSD
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