Date: Tue, 4 Mar 2008 11:27:15 GMT From: "Randall R. Stewart" <rrs@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 136800 for review Message-ID: <200803041127.m24BRFe0088629@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=136800 Change 136800 by rrs@rrs-mips2-jnpr on 2008/03/04 11:26:21 move all PG_XXX to PTE_XXX Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/include/pte.h#6 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/include/pte.h#6 (text+ko) ==== @@ -93,58 +93,57 @@ #define PT_ENTRY_NULL ((pt_entry_t *) 0) -#define PG_WIRED 0x80000000 /* SW */ -#define PG_W PG_WIRED -#define PG_RO 0x40000000 /* SW */ +#define PTE_WIRED 0x80000000 /* SW */ +#define PTE_W PTE_WIRED +#define PTE_RO 0x40000000 /* SW */ + +#define PTE_G 0x00000001 /* HW */ +#define PTE_V 0x00000002 +/*#define PTE_NV 0x00000000 Not Used */ +#define PTE_M 0x00000004 +#define PTE_RW PTE_M +#define PTE_ODDPG 0x00001000 +/*#define PG_ATTR 0x0000003f Not Used */ +#define PTE_UNCACHED 0x00000010 +#define PTE_CACHE 0x00000018 +/*#define PG_CACHEMODE 0x00000038 Not Used*/ +#define PTE_ROPAGE (PTE_V | PTE_RO | PTE_CACHE) /* Write protected */ +#define PTE_RWPAGE (PTE_V | PTE_M | PTE_CACHE) /* Not wr-prot not clean */ +#define PTE_CWPAGE (PTE_V | PTE_CACHE) /* Not wr-prot but clean */ +#define PTE_IOPAGE (PTE_G | PTE_V | PTE_M | PTE_UNCACHED) +#define PTE_FRAME 0x3fffffc0 +#define PTE_HVPN 0xffffe000 /* Hardware page no mask */ +#define PTE_ASID 0x000000ff /* Address space ID */ -#define PG_SVPN 0xfffff000 /* Software page no mask */ -#define PG_HVPN 0xffffe000 /* Hardware page no mask */ -#define PG_ODDPG 0x00001000 /* Odd even pte entry */ -#define PG_ASID 0x000000ff /* Address space ID */ -#define PG_G 0x00000001 /* HW */ -#define PG_V 0x00000002 -#define PG_NV 0x00000000 -#define PG_M 0x00000004 -#define PG_RW PG_M -#define PG_ATTR 0x0000003f -#define PG_UNCACHED 0x00000010 -#define PG_CACHE 0x00000018 -#define PG_CACHEMODE 0x00000038 -#define PG_ROPAGE (PG_V | PG_RO | PG_CACHE) /* Write protected */ -#define PG_RWPAGE (PG_V | PG_M | PG_CACHE) /* Not wr-prot not clean */ -#define PG_CWPAGE (PG_V | PG_CACHED) /* Not wr-prot but clean */ -#define PG_IOPAGE (PG_G | PG_V | PG_M | PG_UNCACHED) -#define PG_FRAME 0x3fffffc0 -#define PG_SHIFT 6 +#define PTE_SHIFT 6 #define pfn_is_ext(x) ((x) & 0x3c000000) -#define vad_to_pfn(x) (((unsigned)(x) >> PG_SHIFT) & PG_FRAME) -#define vad_to_pfn64(x) ((quad_t)(x) >> PG_SHIFT) & PG_FRAME) -#define pfn_to_vad(x) (((x) & PG_FRAME) << PG_SHIFT) -#define vad_to_vpn(x) ((unsigned)(x) & PG_SVPN) -#define vpn_to_vad(x) ((x) & PG_SVPN) +#define vad_to_pfn(x) (((unsigned)(x) >> PTE_SHIFT) & PTE_FRAME) +#define vad_to_pfn64(x) ((quad_t)(x) >> PTE_SHIFT) & PTE_FRAME) +#define pfn_to_vad(x) (((x) & PTE_FRAME) << PTE_SHIFT) + /* User viritual to pte offset in page table */ #define vad_to_pte_offset(adr) (((adr) >> PGSHIFT) & (NPTEPG -1)) -#define mips_pg_v(entry) ((entry) & PG_V) -#define mips_pg_wired(entry) ((entry) & PG_WIRED) -#define mips_pg_m_bit() (PG_M) -#define mips_pg_rw_bit() (PG_M) -#define mips_pg_ro_bit() (PG_RO) -#define mips_pg_ropage_bit() (PG_ROPAGE) -#define mips_pg_rwpage_bit() (PG_RWPAGE) -#define mips_pg_cwpage_bit() (PG_CWPAGE) -#define mips_pg_global_bit() (PG_G) -#define mips_pg_wired_bit() (PG_WIRED) +#define mips_pg_v(entry) ((entry) & PTE_V) +#define mips_pg_wired(entry) ((entry) & PTE_WIRED) +#define mips_pg_m_bit() (PTE_M) +#define mips_pg_rw_bit() (PTE_M) +#define mips_pg_ro_bit() (PTE_RO) +#define mips_pg_ropage_bit() (PTE_ROPAGE) +#define mips_pg_rwpage_bit() (PTE_RWPAGE) +#define mips_pg_cwpage_bit() (PTE_CWPAGE) +#define mips_pg_global_bit() (PTE_G) +#define mips_pg_wired_bit() (PTE_WIRED) #define mips_tlbpfn_to_paddr(x) pfn_to_vad((x)) #define mips_paddr_to_tlbpfn(x) vad_to_pfn((x)) - -#define PG_SIZE_4K 0x00000000 -#define PG_SIZE_16K 0x00006000 -#define PG_SIZE_64K 0x0001e000 -#define PG_SIZE_256K 0x0007e000 -#define PG_SIZE_1M 0x001fe000 -#define PG_SIZE_4M 0x007fe000 -#define PG_SIZE_16M 0x01ffe000 +/* These are not used */ +#define PTE_SIZE_4K 0x00000000 +#define PTE_SIZE_16K 0x00006000 +#define PTE_SIZE_64K 0x0001e000 +#define PTE_SIZE_256K 0x0007e000 +#define PTE_SIZE_1M 0x001fe000 +#define PTE_SIZE_4M 0x007fe000 +#define PTE_SIZE_16M 0x01ffe000 #endif /* !_MACHINE_PTE_H_ */
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