Date: Tue, 24 Mar 2026 10:49:17 -0300 From: Mitchell Horne <mhorne@freebsd.org> To: Oliver Pinter <oliver.pntr@gmail.com> Cc: "src-committers@freebsd.org" <src-committers@freebsd.org>, "dev-commits-src-all@freebsd.org" <dev-commits-src-all@freebsd.org>, "dev-commits-src-main@freebsd.org" <dev-commits-src-main@freebsd.org>, Ali Mashtizadeh <mashti@uwaterloo.ca> Subject: Re: git: df47355fae72 - main - libpmc: Add support for IBS qualifiers Message-ID: <366f1427-0447-4344-bab3-5d700956d6a9@freebsd.org> In-Reply-To: <CAPjTQNG=xAVKitXvuj7Su_yQhrRpHYjRgDW=k3uiSfyah01EdA@mail.gmail.com> References: <69c1a0f7.47fb8.263fa653@gitrepo.freebsd.org> <CAPjTQNG=xAVKitXvuj7Su_yQhrRpHYjRgDW=k3uiSfyah01EdA@mail.gmail.com>
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On 3/23/26 18:12, Oliver Pinter wrote: > > > On Monday, March 23, 2026, Mitchell Horne <mhorne@freebsd.org > <mailto:mhorne@freebsd.org>> wrote: > > The branch main has been updated by mhorne: > > URL: https://cgit.FreeBSD.org/src/commit/? > id=df47355fae720fd8f63f36a50c8933f8342483d2 <https:// > cgit.FreeBSD.org/src/commit/? > id=df47355fae720fd8f63f36a50c8933f8342483d2> > > commit df47355fae720fd8f63f36a50c8933f8342483d2 > Author: Ali Mashtizadeh <mashti@uwaterloo.ca > <mailto:mashti@uwaterloo.ca>> > AuthorDate: 2026-03-18 04:27:09 +0000 > Commit: Mitchell Horne <mhorne@FreeBSD.org> > CommitDate: 2026-03-23 20:21:28 +0000 > > libpmc: Add support for IBS qualifiers > > Add support to libpmc for parsing the IBS qualifiers and > computing the > ctl register value as a function of the qualifiers and the > sample rate. > This includes all of the flags available up to AMD Zen 5. Along > side > these user facing changes I included the documentation for AMD IBS. > > Reviewed by: mhorne > Sponsored by: Netflix > Pull Request: https://github.com/freebsd/freebsd-src/pull/2081 > <https://github.com/freebsd/freebsd-src/pull/2081>; > --- > lib/libpmc/Makefile | 1 + > lib/libpmc/libpmc.c | 71 ++++++++++++++++++---- > lib/libpmc/pmc.3 | 7 +++ > lib/libpmc/pmc.amd.3 | 1 + > lib/libpmc/pmc.core.3 | 1 + > lib/libpmc/pmc.core2.3 | 1 + > lib/libpmc/pmc.iaf.3 | 1 + > lib/libpmc/pmc.ibs.3 | 150 +++++++++++++++++++++++++++++++++++ > +++++++++++ > lib/libpmc/pmc.soft.3 | 1 + > lib/libpmc/pmc.tsc.3 | 1 + > lib/libpmc/pmc.ucf.3 | 1 + > sys/dev/hwpmc/hwpmc_ibs.h | 19 +++++- > 12 files changed, 244 insertions(+), 11 deletions(-) > > diff --git a/lib/libpmc/Makefile b/lib/libpmc/Makefile > index 590f719ebff4..442efdc3d9c0 100644 > --- a/lib/libpmc/Makefile > +++ b/lib/libpmc/Makefile > @@ -74,6 +74,7 @@ MAN+= pmc.haswell.3 > MAN+= pmc.haswelluc.3 > MAN+= pmc.haswellxeon.3 > MAN+= pmc.iaf.3 > +MAN+= pmc.ibs.3 > MAN+= pmc.ivybridge.3 > MAN+= pmc.ivybridgexeon.3 > MAN+= pmc.sandybridge.3 > diff --git a/lib/libpmc/libpmc.c b/lib/libpmc/libpmc.c > index ceba40aa7b39..ebb642e8d16b 100644 > --- a/lib/libpmc/libpmc.c > +++ b/lib/libpmc/libpmc.c > @@ -696,7 +696,7 @@ ibs_allocate_pmc(enum pmc_event pe, char *ctrspec, > struct pmc_op_pmcallocate *pmc_config) > { > char *e, *p, *q; > - uint64_t ctl; > + uint64_t ctl, ldlat; > > pmc_config->pm_caps |= > (PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_PRECISE); > @@ -714,23 +714,74 @@ ibs_allocate_pmc(enum pmc_event pe, char *ctrspec, > return (-1); > } > > + /* IBS only supports sampling mode */ > + if (!PMC_IS_SAMPLING_MODE(pmc_config->pm_mode)) { > + return (-1); > + } > + > /* parse parameters */ > - while ((p = strsep(&ctrspec, ",")) != NULL) { > - if (KWPREFIXMATCH(p, "ctl=")) { > - q = strchr(p, '='); > - if (*++q == '\0') /* skip '=' */ > + ctl = 0; > + if (pe == PMC_EV_IBS_FETCH) { > + while ((p = strsep(&ctrspec, ",")) != NULL) { > + if (KWMATCH(p, "l3miss")) { > + ctl |= IBS_FETCH_CTL_L3MISSONLY; > + } else if (KWMATCH(p, "randomize")) { > + ctl |= IBS_FETCH_CTL_RANDOMIZE; > + } else { > return (-1); > + } > + } > > - ctl = strtoull(q, &e, 0); > - if (e == q || *e != '\0') > + if (pmc_config->pm_count < IBS_FETCH_MIN_RATE || > + pmc_config->pm_count > IBS_FETCH_MAX_RATE) > + return (-1); > + > + ctl |= IBS_FETCH_INTERVAL_TO_CTL(pmc_config->pm_count); > + } else { > + while ((p = strsep(&ctrspec, ",")) != NULL) { > + if (KWMATCH(p, "l3miss")) { > + ctl |= IBS_OP_CTL_L3MISSONLY; > + } else if (KWPREFIXMATCH(p, "ldlat=")) { > + q = strchr(p, '='); > + if (*++q == '\0') /* skip '=' */ > + return (-1); > + > + ldlat = strtoull(q, &e, 0); > + if (e == q || *e != '\0') > + return (-1); > + > + /* > + * IBS load latency filtering > requires the > + * latency to be a multiple of 128 > and between > + * 128 and 2048. The latency is > stored in the > + * IbsOpLatThrsh field, which only > contains > + * four bits so the processor computes > + * (IbsOpLatThrsh+1)*128 as the value. > + * > + * AMD PPR Vol 1 for AMD Family 1Ah > Model 02h > + * C1 (57238) 2026-03-06 Revision 0.49. > + */ > + if (ldlat < 128 || ldlat > 2048) > + return (-1); > + ctl |= IBS_OP_CTL_LDLAT_TO_CTL(ldlat); > + ctl |= IBS_OP_CTL_L3MISSONLY | > IBS_OP_CTL_LATFLTEN; > + } else if (KWMATCH(p, "randomize")) { > + ctl |= IBS_OP_CTL_COUNTERCONTROL; > + } else { > return (-1); > + } > + } > > - pmc_config->pm_md.pm_ibs.ibs_ctl |= ctl; > - } else { > + if (pmc_config->pm_count < IBS_OP_MIN_RATE || > + pmc_config->pm_count > IBS_OP_MAX_RATE) > return (-1); > - } > + > + ctl |= IBS_OP_INTERVAL_TO_CTL(pmc_config->pm_count); > } > > + > + pmc_config->pm_md.pm_ibs.ibs_ctl |= ctl; > + > return (0); > } > > diff --git a/lib/libpmc/pmc.3 b/lib/libpmc/pmc.3 > index 9a5b599759ff..cb28e0b786b9 100644 > --- a/lib/libpmc/pmc.3 > +++ b/lib/libpmc/pmc.3 > @@ -224,6 +224,11 @@ performance measurement architecture version 2 > and later. > Programmable hardware counters present in CPUs conforming to the > .Tn Intel > performance measurement architecture version 1 and later. > +.It Li PMC_CLASS_IBS > +.Tn AMD > +Instruction Based Sampling (IBS) counters present in > +.Tn AMD > +Family 10h and above. > .It Li PMC_CLASS_K8 > Programmable hardware counters present in > .Tn "AMD Athlon64" > @@ -491,6 +496,7 @@ following manual pages: > .It Em "PMC Class" Ta Em "Manual Page" > .It Li PMC_CLASS_IAF Ta Xr pmc.iaf 3 > .It Li PMC_CLASS_IAP Ta Xr pmc.atom 3 , Xr pmc.core 3 , Xr > pmc.core2 3 > +.It Li PMC_CLASS_IBS Ta Xr pmc.ibs 3 > .It Li PMC_CLASS_K8 Ta Xr pmc.amd 3 > .It Li PMC_CLASS_TSC Ta Xr pmc.tsc 3 > .El > @@ -542,6 +548,7 @@ Doing otherwise is unsupported. > .Xr pmc.haswelluc 3 , > .Xr pmc.haswellxeon 3 , > .Xr pmc.iaf 3 , > +.Xr pmc.ibs 3 , > .Xr pmc.ivybridge 3 , > .Xr pmc.ivybridgexeon 3 , > .Xr pmc.sandybridge 3 , > diff --git a/lib/libpmc/pmc.amd.3 b/lib/libpmc/pmc.amd.3 > index 047b31aa78bb..75c6331b000f 100644 > --- a/lib/libpmc/pmc.amd.3 > +++ b/lib/libpmc/pmc.amd.3 > @@ -777,6 +777,7 @@ and the underlying hardware events used. > .Xr pmc.core 3 , > .Xr pmc.core2 3 , > .Xr pmc.iaf 3 , > +.Xr pmc.ibs 3 , > .Xr pmc.soft 3 , > .Xr pmc.tsc 3 , > .Xr pmclog 3 , > diff --git a/lib/libpmc/pmc.core.3 b/lib/libpmc/pmc.core.3 > index b4fa9ab661a4..4c41e7c7ad3b 100644 > --- a/lib/libpmc/pmc.core.3 > +++ b/lib/libpmc/pmc.core.3 > @@ -786,6 +786,7 @@ may not count some transitions. > .Xr pmc.atom 3 , > .Xr pmc.core2 3 , > .Xr pmc.iaf 3 , > +.Xr pmc.ibs 3 , > .Xr pmc.soft 3 , > .Xr pmc.tsc 3 , > .Xr pmclog 3 , > diff --git a/lib/libpmc/pmc.core2.3 b/lib/libpmc/pmc.core2.3 > index 86604b7ff16c..7e544fad43b6 100644 > --- a/lib/libpmc/pmc.core2.3 > +++ b/lib/libpmc/pmc.core2.3 > @@ -1101,6 +1101,7 @@ and the underlying hardware events used. > .Xr pmc.atom 3 , > .Xr pmc.core 3 , > .Xr pmc.iaf 3 , > +.Xr pmc.ibs 3 , > .Xr pmc.soft 3 , > .Xr pmc.tsc 3 , > .Xr pmc_cpuinfo 3 , > diff --git a/lib/libpmc/pmc.iaf.3 b/lib/libpmc/pmc.iaf.3 > index eaf45db140f5..c3528e472103 100644 > --- a/lib/libpmc/pmc.iaf.3 > +++ b/lib/libpmc/pmc.iaf.3 > @@ -125,6 +125,7 @@ CPU, use the event specifier > .Xr pmc.atom 3 , > .Xr pmc.core 3 , > .Xr pmc.core2 3 , > +.Xr pmc.ibs 3 , > .Xr pmc.soft 3 , > .Xr pmc.tsc 3 , > .Xr pmc_cpuinfo 3 , > diff --git a/lib/libpmc/pmc.ibs.3 b/lib/libpmc/pmc.ibs.3 > new file mode 100644 > index 000000000000..69b90b84556c > --- /dev/null > +++ b/lib/libpmc/pmc.ibs.3 > @@ -0,0 +1,150 @@ > +.\" Copyright (c) 2016 Ali Mashtizadeh. All rights reserved. > > > Isn't this 2026? > Yes, it should be. Thanks for pointing this out. Looks like it is missing the SPDX tag as well. I will confer with the author and fix it. Cheers, Mitchellhome | help
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