Date: Wed, 20 May 2009 17:21:14 GMT From: John Baldwin <jhb@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 162377 for review Message-ID: <200905201721.n4KHLEcC086559@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=162377 Change 162377 by jhb@jhb_jhbbsd on 2009/05/20 17:20:32 IFC @162374 Affected files ... .. //depot/projects/smpng/sys/amd64/amd64/mca.c#2 integrate .. //depot/projects/smpng/sys/dev/age/if_age.c#7 integrate .. //depot/projects/smpng/sys/dev/ata/chipsets/ata-promise.c#7 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ah.c#9 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ah.h#6 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ah_internal.h#8 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ar5210/ar5210_attach.c#5 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c#2 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ar5211/ar5211_attach.c#5 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c#3 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c#5 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c#3 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ar5212/ar5212reg.h#2 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c#4 integrate .. //depot/projects/smpng/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c#4 integrate .. //depot/projects/smpng/sys/dev/usb/controller/atmegadci.c#7 integrate .. //depot/projects/smpng/sys/dev/usb/controller/atmegadci.h#5 integrate .. //depot/projects/smpng/sys/dev/usb/controller/uss820dci.c#6 integrate .. //depot/projects/smpng/sys/dev/usb/controller/uss820dci.h#5 integrate .. //depot/projects/smpng/sys/dev/usb/controller/uss820dci_atmelarm.c#5 integrate .. //depot/projects/smpng/sys/dev/usb/wlan/if_uath.c#4 integrate .. //depot/projects/smpng/sys/dev/usb/wlan/if_upgt.c#2 integrate .. //depot/projects/smpng/sys/i386/acpica/acpi_machdep.c#31 integrate .. //depot/projects/smpng/sys/i386/bios/smapi.c#10 integrate .. //depot/projects/smpng/sys/i386/i386/mca.c#2 integrate .. //depot/projects/smpng/sys/kern/kern_poll.c#32 integrate .. //depot/projects/smpng/sys/kern/subr_bus.c#78 integrate .. //depot/projects/smpng/sys/kern/subr_rman.c#40 integrate .. //depot/projects/smpng/sys/kern/subr_witness.c#180 integrate .. //depot/projects/smpng/sys/netnatm/natm.c#32 integrate .. //depot/projects/smpng/sys/nfs4client/nfs4_dev.c#10 integrate Differences ... ==== //depot/projects/smpng/sys/amd64/amd64/mca.c#2 (text+ko) ==== @@ -30,7 +30,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/amd64/amd64/mca.c,v 1.2 2009/05/18 21:50:06 jhb Exp $"); +__FBSDID("$FreeBSD: src/sys/amd64/amd64/mca.c,v 1.3 2009/05/20 16:11:22 jhb Exp $"); #include <sys/param.h> #include <sys/kernel.h> @@ -491,10 +491,6 @@ if (!(i == 0 && (cpu_id & 0xf00) == 0x600)) wrmsr(MSR_MC_CTL(i), 0xffffffffffffffffUL); - /* XXX: Better CPU test needed here. */ - if ((cpu_id & 0xf00) == 0xf00) - mca_record_entry(i); - /* Clear all errors. */ wrmsr(MSR_MC_STATUS(i), 0); } ==== //depot/projects/smpng/sys/dev/age/if_age.c#7 (text+ko) ==== @@ -28,7 +28,7 @@ /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/dev/age/if_age.c,v 1.8 2009/03/28 07:39:35 yongari Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/age/if_age.c,v 1.9 2009/05/20 03:33:27 yongari Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -1477,23 +1477,11 @@ { struct age_softc *sc; struct ifnet *ifp; - uint16_t cmd; sc = device_get_softc(dev); AGE_LOCK(sc); - /* - * Clear INTx emulation disable for hardwares that - * is set in resume event. From Linux. - */ - cmd = pci_read_config(sc->age_dev, PCIR_COMMAND, 2); - if ((cmd & 0x0400) != 0) { - cmd &= ~0x0400; - pci_write_config(sc->age_dev, PCIR_COMMAND, cmd, 2); - } - AGE_UNLOCK(sc); age_phy_reset(sc); - AGE_LOCK(sc); ifp = sc->age_ifp; if ((ifp->if_flags & IFF_UP) != 0) age_init_locked(sc); ==== //depot/projects/smpng/sys/dev/ata/chipsets/ata-promise.c#7 (text+ko) ==== @@ -25,7 +25,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/dev/ata/chipsets/ata-promise.c,v 1.9 2009/05/14 14:57:13 jhb Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/ata/chipsets/ata-promise.c,v 1.10 2009/05/20 09:44:32 mav Exp $"); #include "opt_ata.h" #include <sys/param.h> @@ -1054,7 +1054,7 @@ device_t gparent = GRANDPARENT(request->dev); struct ata_pci_controller *ctlr = device_get_softc(gparent); struct ata_channel *ch = device_get_softc(request->parent); - struct ata_dma_prdentry *prd = request->dma->sg; + struct ata_dma_prdentry *prd; caddr_t window = rman_get_virtual(ctlr->r_res1); u_int32_t *wordp; int i, idx, length = 0; @@ -1098,6 +1098,7 @@ case ATA_READ_DMA48: case ATA_WRITE_DMA: case ATA_WRITE_DMA48: + prd = request->dma->sg; wordp = (u_int32_t *) (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); i = idx = 0; ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ah.c#9 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $FreeBSD: src/sys/dev/ath/ath_hal/ah.c,v 1.9 2009/04/13 21:01:08 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ah.c,v 1.10 2009/05/19 17:30:13 sam Exp $ */ #include "opt_ah.h" @@ -500,6 +500,9 @@ case HAL_CAP_RXTSTAMP_PREC: /* rx desc tstamp precision (bits) */ *result = pCap->halTstampPrecision; return HAL_OK; + case HAL_CAP_INTRMASK: /* mask of supported interrupts */ + *result = pCap->halIntrMask; + return HAL_OK; default: return HAL_EINVAL; } ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ah.h#6 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $FreeBSD: src/sys/dev/ath/ath_hal/ah.h,v 1.7 2009/03/19 19:29:10 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ah.h,v 1.11 2009/05/19 17:54:32 sam Exp $ */ #ifndef _ATH_AH_H_ @@ -109,6 +109,7 @@ HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */ HAL_CAP_BB_HANG = 35, /* can baseband hang */ HAL_CAP_MAC_HANG = 36, /* can MAC hang */ + HAL_CAP_INTRMASK = 37, /* bitmask of supported interrupts */ } HAL_CAPABILITY_TYPE; /* @@ -327,13 +328,14 @@ HAL_INT_RXKCM = 0x00008000, HAL_INT_SWBA = 0x00010000, HAL_INT_BMISS = 0x00040000, - HAL_INT_BNR = 0x00100000, /* Non-common mapping */ + HAL_INT_BNR = 0x00100000, HAL_INT_TIM = 0x00200000, /* Non-common mapping */ HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ HAL_INT_GPIO = 0x01000000, HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ + HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ HAL_INT_CST = 0x10000000, /* Non-common mapping */ HAL_INT_GTT = 0x20000000, /* Non-common mapping */ HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ @@ -341,20 +343,22 @@ HAL_INT_BMISC = HAL_INT_TIM | HAL_INT_DTIM | HAL_INT_DTIMSYNC - | HAL_INT_CABEND, + | HAL_INT_CABEND + | HAL_INT_TBTT, /* Interrupt bits that map directly to ISR/IMR bits */ HAL_INT_COMMON = HAL_INT_RXNOFRM | HAL_INT_RXDESC | HAL_INT_RXEOL | HAL_INT_RXORN + | HAL_INT_TXDESC | HAL_INT_TXURN - | HAL_INT_TXDESC | HAL_INT_MIB | HAL_INT_RXPHY | HAL_INT_RXKCM | HAL_INT_SWBA | HAL_INT_BMISS + | HAL_INT_BNR | HAL_INT_GPIO, } HAL_INT; ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ah_internal.h#8 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $FreeBSD: src/sys/dev/ath/ath_hal/ah_internal.h,v 1.11 2009/04/09 16:53:59 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ah_internal.h,v 1.12 2009/05/19 17:30:13 sam Exp $ */ #ifndef _ATH_AH_INTERAL_H_ #define _ATH_AH_INTERAL_H_ @@ -206,6 +206,7 @@ uint8_t halNumGpioPins; uint8_t halNumAntCfg2GHz; uint8_t halNumAntCfg5GHz; + uint32_t halIntrMask; } HAL_CAPABILITIES; struct regDomain; ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ar5210/ar5210_attach.c#5 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $FreeBSD: src/sys/dev/ath/ath_hal/ar5210/ar5210_attach.c,v 1.5 2009/03/19 19:29:10 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ar5210/ar5210_attach.c,v 1.7 2009/05/19 17:35:15 sam Exp $ */ #include "opt_ah.h" @@ -369,6 +369,11 @@ } pCap->halTstampPrecision = 15; /* NB: s/w extended from 13 */ + pCap->halIntrMask = (HAL_INT_COMMON - HAL_INT_BNR) + | HAL_INT_RX + | HAL_INT_TX + | HAL_INT_FATAL + ; ahpriv->ah_rxornIsFatal = AH_TRUE; return AH_TRUE; ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c#2 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id: ar5210_interrupts.c,v 1.4 2008/11/10 04:08:02 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c,v 1.2 2009/05/19 17:35:15 sam Exp $ */ #include "opt_ah.h" @@ -59,7 +59,7 @@ * status bits leak through that weren't requested * (e.g. RXNOFRM) and that might confuse the caller. */ - *masked = (isr & HAL_INT_COMMON) & ahp->ah_maskReg; + *masked = (isr & (HAL_INT_COMMON - HAL_INT_BNR)) & ahp->ah_maskReg; if (isr & AR_FATAL_INT) *masked |= HAL_INT_FATAL; @@ -105,7 +105,7 @@ OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); } - mask = ints & HAL_INT_COMMON; + mask = ints & (HAL_INT_COMMON - HAL_INT_BNR); if (ints & HAL_INT_RX) mask |= AR_IMR_RXOK_INT | AR_IMR_RXERR_INT; if (ints & HAL_INT_TX) { ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ar5211/ar5211_attach.c#5 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $FreeBSD: src/sys/dev/ath/ath_hal/ar5211/ar5211_attach.c,v 1.6 2009/03/19 19:29:10 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ar5211/ar5211_attach.c,v 1.7 2009/05/19 17:30:13 sam Exp $ */ #include "opt_ah.h" @@ -498,6 +498,13 @@ } pCap->halTstampPrecision = 13; + pCap->halIntrMask = HAL_INT_COMMON + | HAL_INT_RX + | HAL_INT_TX + | HAL_INT_FATAL + | HAL_INT_BNR + | HAL_INT_TIM + ; /* XXX might be ok w/ some chip revs */ ahpriv->ah_rxornIsFatal = AH_TRUE; ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c#3 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $FreeBSD: src/sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c,v 1.2 2009/05/06 23:09:26 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c,v 1.3 2009/05/19 17:35:15 sam Exp $ */ #include "opt_ah.h" @@ -64,8 +64,6 @@ *masked |= HAL_INT_RX; if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) *masked |= HAL_INT_TX; - if (isr & AR_ISR_BNR) - *masked |= HAL_INT_BNR; /* * Receive overrun is usually non-fatal on Oahu/Spirit. * BUT on some parts rx could fail and the chip must be reset. @@ -139,8 +137,6 @@ } if (ints & HAL_INT_RX) mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; - if (ints & AR_ISR_BNR) - mask |= HAL_INT_BNR; if (ints & HAL_INT_FATAL) { /* * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2 ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c#5 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $FreeBSD: src/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c,v 1.5 2009/03/19 19:29:10 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c,v 1.7 2009/05/19 17:53:53 sam Exp $ */ #include "opt_ah.h" @@ -840,6 +840,15 @@ AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE; pCap->halTstampPrecision = 15; + pCap->halIntrMask = HAL_INT_COMMON + | HAL_INT_RX + | HAL_INT_TX + | HAL_INT_FATAL + | HAL_INT_BNR + | HAL_INT_BMISC + ; + if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) + pCap->halIntrMask &= ~HAL_INT_TBTT; return AH_TRUE; #undef IS_COBRA ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c#3 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $FreeBSD: src/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c,v 1.2 2009/05/06 23:09:26 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c,v 1.5 2009/05/19 17:53:53 sam Exp $ */ #include "opt_ah.h" @@ -55,21 +55,23 @@ ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) { uint32_t isr, isr0, isr1; - uint32_t mask2=0; + uint32_t mask2; struct ath_hal_5212 *ahp = AH5212(ah); isr = OS_REG_READ(ah, AR_ISR); + mask2 = 0; if (isr & AR_ISR_BCNMISC) { - uint32_t isr2; - isr2 = OS_REG_READ(ah, AR_ISR_S2); + uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2); if (isr2 & AR_ISR_S2_TIM) mask2 |= HAL_INT_TIM; if (isr2 & AR_ISR_S2_DTIM) mask2 |= HAL_INT_DTIM; if (isr2 & AR_ISR_S2_DTIMSYNC) mask2 |= HAL_INT_DTIMSYNC; - if (isr2 & (AR_ISR_S2_CABEND )) + if (isr2 & AR_ISR_S2_CABEND) mask2 |= HAL_INT_CABEND; + if (isr2 & AR_ISR_S2_TBTT) + mask2 |= HAL_INT_TBTT; } isr = OS_REG_READ(ah, AR_ISR_RAC); if (isr == 0xffffffff) { @@ -92,8 +94,6 @@ ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR); ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); } - if (isr & AR_ISR_BNR) - *masked |= HAL_INT_BNR; /* * Receive overrun is usually non-fatal on Oahu/Spirit. @@ -139,7 +139,7 @@ { struct ath_hal_5212 *ahp = AH5212(ah); uint32_t omask = ahp->ah_maskReg; - uint32_t mask,mask2; + uint32_t mask, mask2; HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__, omask, ints); @@ -173,10 +173,10 @@ if (ints & HAL_INT_DTIMSYNC) mask2 |= AR_IMR_S2_DTIMSYNC; if (ints & HAL_INT_CABEND) - mask2 |= (AR_IMR_S2_CABEND ); + mask2 |= AR_IMR_S2_CABEND; + if (ints & HAL_INT_TBTT) + mask2 |= AR_IMR_S2_TBTT; } - if (ints & HAL_INT_BNR) - mask |= AR_IMR_BNR; if (ints & HAL_INT_FATAL) { /* * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2 @@ -188,15 +188,8 @@ /* Write the new IMR and store off our SW copy. */ HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); OS_REG_WRITE(ah, AR_IMR, mask); - OS_REG_WRITE(ah, AR_IMR_S2, - (OS_REG_READ(ah, AR_IMR_S2) & - ~(AR_IMR_S2_TIM | - AR_IMR_S2_DTIM | - AR_IMR_S2_DTIMSYNC | - AR_IMR_S2_CABEND | - AR_IMR_S2_CABTO | - AR_IMR_S2_TSFOOR ) ) - | mask2); + OS_REG_WRITE(ah, AR_IMR_S2, + (OS_REG_READ(ah, AR_IMR_S2) &~ AR_IMR_SR2_BCNMISC) | mask2); ahp->ah_maskReg = ints; /* Re-enable interrupts if they were enabled before. */ @@ -204,7 +197,5 @@ HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); } - - return omask; } ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ar5212/ar5212reg.h#2 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id: ar5212reg.h,v 1.5 2008/11/16 06:45:43 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ar5212/ar5212reg.h,v 1.3 2009/05/19 17:53:53 sam Exp $ */ #ifndef _DEV_ATH_AR5212REG_H_ #define _DEV_ATH_AR5212REG_H_ @@ -463,7 +463,8 @@ #define AR_ISR_S2_BCNTO 0x08000000 /* BCNTO */ #define AR_ISR_S2_CABTO 0x10000000 /* CABTO */ #define AR_ISR_S2_DTIM 0x20000000 /* DTIM */ -#define AR_ISR_S2_RESV0 0xE0F8FC00 /* Reserved */ +#define AR_ISR_S2_TSFOOR 0x40000000 /* TSF OOR */ +#define AR_ISR_S2_TBTT 0x80000000 /* TBTT timer */ #define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ @@ -531,8 +532,14 @@ #define AR_IMR_S2_BCNTO 0x08000000 /* BCNTO */ #define AR_IMR_S2_CABTO 0x10000000 /* CABTO */ #define AR_IMR_S2_DTIM 0x20000000 /* DTIM */ -#define AR_IMR_S2_TSFOOR 0x80000000 /* TSF OOR */ -#define AR_IMR_S2_RESV0 0xE0F8FC00 /* Reserved */ +#define AR_IMR_S2_TSFOOR 0x40000000 /* TSF OOR */ +#define AR_IMR_S2_TBTT 0x80000000 /* TBTT timer */ + +/* AR_IMR_SR2 bits that correspond to AR_IMR_BCNMISC */ +#define AR_IMR_SR2_BCNMISC \ + (AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | \ + AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR | \ + AR_IMR_S2_TBTT) #define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c#4 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $FreeBSD: src/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c,v 1.8 2009/03/12 18:18:28 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c,v 1.9 2009/05/19 17:30:13 sam Exp $ */ #include "opt_ah.h" @@ -781,6 +781,17 @@ pCap->halTstampPrecision = 32; pCap->halHwPhyCounterSupport = AH_TRUE; + pCap->halIntrMask = HAL_INT_COMMON + | HAL_INT_RX + | HAL_INT_TX + | HAL_INT_FATAL + | HAL_INT_BNR + | HAL_INT_BMISC + | HAL_INT_DTIMSYNC + | HAL_INT_TSFOOR + | HAL_INT_CST + | HAL_INT_GTT + ; pCap->halFastCCSupport = AH_TRUE; pCap->halNumGpioPins = 6; ==== //depot/projects/smpng/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c#4 (text+ko) ==== @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $FreeBSD: src/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c,v 1.3 2009/05/06 23:09:26 sam Exp $ + * $FreeBSD: src/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c,v 1.4 2009/05/19 17:35:15 sam Exp $ */ #include "opt_ah.h" @@ -119,8 +119,6 @@ ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR); ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); } - if (isr & AR_ISR_BNR) - *masked |= HAL_INT_BNR; /* Interrupt Mitigation on AR5416 */ #ifdef AR5416_INT_MITIGATION @@ -229,8 +227,6 @@ if (ints & HAL_INT_TSFOOR) mask2 |= AR_IMR_S2_TSFOOR; } - if (ints & HAL_INT_BNR) - mask |= AR_IMR_BNR; /* Write the new IMR and store off our SW copy. */ HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); ==== //depot/projects/smpng/sys/dev/usb/controller/atmegadci.c#7 (text+ko) ==== @@ -1,5 +1,5 @@ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/dev/usb/controller/atmegadci.c,v 1.17 2009/04/22 17:08:16 thompsa Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/usb/controller/atmegadci.c,v 1.18 2009/05/20 17:00:55 thompsa Exp $"); /*- * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. @@ -672,7 +672,7 @@ * that like RESUME. Resume is set when there is at least 3 * milliseconds of inactivity on the USB BUS. */ - if (status & ATMEGA_UDINT_EORSMI) { + if (status & ATMEGA_UDINT_WAKEUPI) { DPRINTFN(5, "resume interrupt\n"); @@ -700,7 +700,7 @@ /* disable suspend interrupt */ ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, - ATMEGA_UDINT_EORSMI | + ATMEGA_UDINT_WAKEUPE | ATMEGA_UDINT_EORSTE); /* complete root HUB interrupt endpoint */ @@ -1152,13 +1152,12 @@ ATMEGA_UECONX_STALLRQC); do { - temp = 0; if (ep_type == UE_BULK) { - temp |= ATMEGA_UECFG0X_EPTYPE2; + temp = ATMEGA_UECFG0X_EPTYPE2; } else if (ep_type == UE_INTERRUPT) { - temp |= ATMEGA_UECFG0X_EPTYPE3; + temp = ATMEGA_UECFG0X_EPTYPE3; } else { - temp |= ATMEGA_UECFG0X_EPTYPE1; + temp = ATMEGA_UECFG0X_EPTYPE1; } if (ep_dir & UE_DIR_IN) { temp |= ATMEGA_UECFG0X_EPDIR; @@ -1217,13 +1216,28 @@ sc->sc_bus.methods = &atmegadci_bus_methods; USB_BUS_LOCK(&sc->sc_bus); -#if 0 - /* XXX TODO - currently done by boot strap */ + + /* make sure USB is enabled */ + ATMEGA_WRITE_1(sc, ATMEGA_USBCON, + ATMEGA_USBCON_USBE | + ATMEGA_USBCON_FRZCLK); /* enable USB PAD regulator */ ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, - ATMEGA_UHWCON_UVREGE | ATMEGA_UHWCON_UIMOD); -#endif + ATMEGA_UHWCON_UVREGE | + ATMEGA_UHWCON_UIMOD); + + /* the following register sets up the USB PLL, assuming 16MHz X-tal */ + ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02); + + /* wait for PLL to lock */ + for (n = 0; n != 20; n++) { + if (ATMEGA_READ_1(sc, 0x49) & 0x01) + break; + /* wait a little bit for PLL to start */ + usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); + } + /* make sure USB is enabled */ ATMEGA_WRITE_1(sc, ATMEGA_USBCON, ATMEGA_USBCON_USBE | @@ -1847,6 +1861,11 @@ /* clear connect change flag */ sc->sc_flags.change_connect = 0; + if (!sc->sc_flags.status_bus_reset) { + /* we are not connected */ + break; + } + /* configure the control endpoint */ /* select endpoint number */ ==== //depot/projects/smpng/sys/dev/usb/controller/atmegadci.h#5 (text+ko) ==== @@ -1,4 +1,4 @@ -/* $FreeBSD: src/sys/dev/usb/controller/atmegadci.h,v 1.5 2009/04/22 17:08:07 thompsa Exp $ */ +/* $FreeBSD: src/sys/dev/usb/controller/atmegadci.h,v 1.6 2009/05/20 17:00:55 thompsa Exp $ */ /*- * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. * @@ -34,6 +34,10 @@ #define ATMEGA_MAX_DEVICES (USB_MIN_DEVICES + 1) +#define ATMEGA_OTGTCON 0xF9 +#define ATMEGA_OTGTCON_VALUE(x) ((x) << 0) +#define ATMEGA_OTGTCON_PAGE(x) ((x) << 5) + #define ATMEGA_UEINT 0xF4 #define ATMEGA_UEINT_MASK(n) (1 << (n)) /* endpoint interrupt mask */ @@ -136,8 +140,19 @@ #define ATMEGA_UDCON_LSM (1 << 2) #define ATMEGA_UDCON_RSTCPU (1 << 3) +#define ATMEGA_OTGINT 0xDF + +#define ATMEGA_OTGCON 0xDD +#define ATMEGA_OTGCON_VBUSRQC (1 << 0) +#define ATMEGA_OTGCON_VBUSREQ (1 << 1) +#define ATMEGA_OTGCON_VBUSHWC (1 << 2) +#define ATMEGA_OTGCON_SRPSEL (1 << 3) +#define ATMEGA_OTGCON_SRPREQ (1 << 4) +#define ATMEGA_OTGCON_HNPREQ (1 << 5) + #define ATMEGA_USBINT 0xDA #define ATMEGA_USBINT_VBUSTI (1 << 0) /* USB VBUS interrupt */ +#define ATMEGA_USBINT_IDI (1 << 1) /* USB ID interrupt */ #define ATMEGA_USBSTA 0xD9 #define ATMEGA_USBSTA_VBUS (1 << 0) @@ -145,6 +160,7 @@ #define ATMEGA_USBCON 0xD8 #define ATMEGA_USBCON_VBUSTE (1 << 0) +#define ATMEGA_USBCON_IDE (1 << 1) #define ATMEGA_USBCON_OTGPADE (1 << 4) #define ATMEGA_USBCON_FRZCLK (1 << 5) #define ATMEGA_USBCON_USBE (1 << 7) ==== //depot/projects/smpng/sys/dev/usb/controller/uss820dci.c#6 (text+ko) ==== @@ -1,4 +1,4 @@ -/* $FreeBSD: src/sys/dev/usb/controller/uss820dci.c,v 1.14 2009/04/22 17:08:16 thompsa Exp $ */ +/* $FreeBSD: src/sys/dev/usb/controller/uss820dci.c,v 1.15 2009/05/20 17:03:12 thompsa Exp $ */ /*- * Copyright (c) 2008 Hans Petter Selasky <hselasky@FreeBSD.org> * All rights reserved. @@ -230,11 +230,11 @@ /* select the correct endpoint */ bus_space_write_1(td->io_tag, td->io_hdl, - td->ep_reg, td->ep_index); + USS820_EPINDEX, td->ep_index); /* read out FIFO status */ rx_stat = bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_stat_reg); + USS820_RXSTAT); /* get pointer to softc */ sc = USS820_DCI_PC2SC(td->pc); @@ -260,9 +260,9 @@ /* get the packet byte count */ count = bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_count_low_reg); + USS820_RXCNTL); count |= (bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_count_high_reg) << 8); + USS820_RXCNTH) << 8); count &= 0x3FF; /* verify data length */ @@ -278,11 +278,11 @@ } /* receive data */ bus_space_read_multi_1(td->io_tag, td->io_hdl, - td->rx_fifo_reg, (void *)&req, sizeof(req)); + USS820_RXDAT, (void *)&req, sizeof(req)); /* read out FIFO status */ rx_stat = bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_stat_reg); + USS820_RXSTAT); if (rx_stat & (USS820_RXSTAT_EDOVW | USS820_RXSTAT_STOVW)) { @@ -297,10 +297,10 @@ /* set RXFFRC bit */ temp = bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_cntl_reg); + USS820_RXCON); temp |= USS820_RXCON_RXFFRC; bus_space_write_1(td->io_tag, td->io_hdl, - td->rx_cntl_reg, temp); + USS820_RXCON, temp); /* copy data into real buffer */ usb2_copy_in(td->pc, 0, &req, sizeof(req)); @@ -321,10 +321,10 @@ /* set RXFFRC bit */ temp = bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_cntl_reg); + USS820_RXCON); temp |= USS820_RXCON_RXFFRC; bus_space_write_1(td->io_tag, td->io_hdl, - td->rx_cntl_reg, temp); + USS820_RXCON, temp); /* FALLTHROUGH */ @@ -365,16 +365,16 @@ got_short = 0; /* select the correct endpoint */ - bus_space_write_1(td->io_tag, td->io_hdl, td->ep_reg, td->ep_index); + bus_space_write_1(td->io_tag, td->io_hdl, USS820_EPINDEX, td->ep_index); /* check if any of the FIFO banks have data */ repeat: /* read out FIFO flag */ rx_flag = bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_flag_reg); + USS820_RXFLG); /* read out FIFO status */ rx_stat = bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_stat_reg); + USS820_RXSTAT); DPRINTFN(5, "rx_stat=0x%02x rx_flag=0x%02x rem=%u\n", rx_stat, rx_flag, td->remainder); @@ -419,10 +419,10 @@ } /* get the packet byte count */ count = bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_count_low_reg); + USS820_RXCNTL); count |= (bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_count_high_reg) << 8); + USS820_RXCNTH) << 8); count &= 0x3FF; DPRINTFN(5, "count=0x%04x\n", count); @@ -454,7 +454,7 @@ } /* receive data */ bus_space_read_multi_1(td->io_tag, td->io_hdl, - td->rx_fifo_reg, buf_res.buffer, buf_res.length); + USS820_RXDAT, buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; @@ -464,10 +464,10 @@ /* set RXFFRC bit */ rx_cntl = bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_cntl_reg); + USS820_RXCON); rx_cntl |= USS820_RXCON_RXFFRC; bus_space_write_1(td->io_tag, td->io_hdl, - td->rx_cntl_reg, rx_cntl); + USS820_RXCON, rx_cntl); /* check if we are complete */ if ((td->remainder == 0) || got_short) { @@ -495,18 +495,18 @@ /* select the correct endpoint */ bus_space_write_1(td->io_tag, td->io_hdl, - td->ep_reg, td->ep_index); + USS820_EPINDEX, td->ep_index); to = 2; /* don't loop forever! */ repeat: /* read out TX FIFO flags */ tx_flag = bus_space_read_1(td->io_tag, td->io_hdl, - td->tx_flag_reg); + USS820_TXFLG); /* read out RX FIFO status last */ rx_stat = bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_stat_reg); + USS820_RXSTAT); DPRINTFN(5, "rx_stat=0x%02x tx_flag=0x%02x rem=%u\n", rx_stat, tx_flag, td->remainder); @@ -553,7 +553,7 @@ } /* transmit data */ bus_space_write_multi_1(td->io_tag, td->io_hdl, - td->tx_fifo_reg, buf_res.buffer, buf_res.length); + USS820_TXDAT, buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; @@ -563,11 +563,11 @@ /* post-write high packet byte count first */ bus_space_write_1(td->io_tag, td->io_hdl, - td->tx_count_high_reg, count_copy >> 8); + USS820_TXCNTH, count_copy >> 8); /* post-write low packet byte count last */ bus_space_write_1(td->io_tag, td->io_hdl, - td->tx_count_low_reg, count_copy); + USS820_TXCNTL, count_copy); /* * Enable TX output, which must happen after that we have written @@ -600,15 +600,15 @@ /* select the correct endpoint */ bus_space_write_1(td->io_tag, td->io_hdl, - td->ep_reg, td->ep_index); + USS820_EPINDEX, td->ep_index); /* read out TX FIFO flag */ tx_flag = bus_space_read_1(td->io_tag, td->io_hdl, - td->tx_flag_reg); + USS820_TXFLG); /* read out RX FIFO status last */ rx_stat = bus_space_read_1(td->io_tag, td->io_hdl, - td->rx_stat_reg); + USS820_RXSTAT); DPRINTFN(5, "rx_stat=0x%02x rem=%u\n", rx_stat, td->remainder); @@ -2269,20 +2269,6 @@ td->io_tag = sc->sc_io_tag; td->io_hdl = sc->sc_io_hdl; td->max_packet_size = xfer->max_packet_size; - td->rx_stat_reg = USS820_GET_REG(sc, USS820_RXSTAT); - td->tx_stat_reg = USS820_GET_REG(sc, USS820_TXSTAT); - td->rx_flag_reg = USS820_GET_REG(sc, USS820_RXFLG); - td->tx_flag_reg = USS820_GET_REG(sc, USS820_TXFLG); - td->rx_fifo_reg = USS820_GET_REG(sc, USS820_RXDAT); - td->tx_fifo_reg = USS820_GET_REG(sc, USS820_TXDAT); - td->rx_count_low_reg = USS820_GET_REG(sc, USS820_RXCNTL); - td->rx_count_high_reg = USS820_GET_REG(sc, USS820_RXCNTH); - td->tx_count_low_reg = USS820_GET_REG(sc, USS820_TXCNTL); - td->tx_count_high_reg = USS820_GET_REG(sc, USS820_TXCNTH); - td->rx_cntl_reg = USS820_GET_REG(sc, USS820_RXCON); - td->tx_cntl_reg = USS820_GET_REG(sc, USS820_TXCON); - td->pend_reg = USS820_GET_REG(sc, USS820_PEND); - td->ep_reg = USS820_GET_REG(sc, USS820_EPINDEX); td->ep_index = ep_no; if (pf->support_multi_buffer && (parm->methods != &uss820dci_device_ctrl_methods)) { ==== //depot/projects/smpng/sys/dev/usb/controller/uss820dci.h#5 (text+ko) ==== @@ -1,4 +1,4 @@ -/* $FreeBSD: src/sys/dev/usb/controller/uss820dci.h,v 1.4 2009/04/22 17:08:07 thompsa Exp $ */ +/* $FreeBSD: src/sys/dev/usb/controller/uss820dci.h,v 1.5 2009/05/20 17:03:12 thompsa Exp $ */ /*- * Copyright (c) 2007 Hans Petter Selasky <hselasky@FreeBSD.org> * All rights reserved. @@ -255,16 +255,11 @@ #define USS820_UNK1 0x1f /* Unknown */ #define USS820_UNK1_UNKNOWN 0xFF -#define USS820_GET_REG(sc,reg) \ - ((reg) << (sc)->sc_reg_shift) - #define USS820_READ_1(sc, reg) \ - bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \ - USS820_GET_REG(sc,reg)) + bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) #define USS820_WRITE_1(sc, reg, data) \ - bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \ - USS820_GET_REG(sc,reg), data) + bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) struct uss820dci_td; @@ -279,20 +274,6 @@ uint32_t offset; uint32_t remainder; uint16_t max_packet_size; - uint8_t rx_stat_reg; - uint8_t tx_stat_reg; - uint8_t rx_flag_reg; - uint8_t tx_flag_reg; - uint8_t rx_fifo_reg; - uint8_t tx_fifo_reg; - uint8_t rx_count_low_reg; - uint8_t rx_count_high_reg; - uint8_t tx_count_low_reg; - uint8_t tx_count_high_reg; - uint8_t rx_cntl_reg; - uint8_t tx_cntl_reg; - uint8_t ep_reg; - uint8_t pend_reg; uint8_t ep_index; uint8_t error:1; uint8_t alt_next:1; @@ -356,7 +337,6 @@ uint8_t sc_rt_addr; /* root HUB address */ uint8_t sc_dv_addr; /* device address */ uint8_t sc_conf; /* root HUB config */ - uint8_t sc_reg_shift; uint8_t sc_hub_idata[1]; ==== //depot/projects/smpng/sys/dev/usb/controller/uss820dci_atmelarm.c#5 (text+ko) ==== @@ -1,5 +1,5 @@ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/dev/usb/controller/uss820dci_atmelarm.c,v 1.5 2009/04/06 00:32:54 thompsa Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/usb/controller/uss820dci_atmelarm.c,v 1.6 2009/05/20 16:58:53 thompsa Exp $"); /*- * Copyright (c) 2008 Hans Petter Selasky <hselasky@FreeBSD.org> @@ -152,9 +152,6 @@ sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); - /* multiply all addresses by 4 */ - sc->sc_reg_shift = 2; - rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); ==== //depot/projects/smpng/sys/dev/usb/wlan/if_uath.c#4 (text+ko) ==== @@ -49,7 +49,7 @@ */ >>> TRUNCATED FOR MAIL (1000 lines) <<<home | help
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