Date: Fri, 24 Feb 2012 18:56:21 +0000 (UTC) From: Olivier Houchard <cognet@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r232121 - projects/armv6/sys/arm/ti/omap4/pandaboard Message-ID: <201202241856.q1OIuLex079575@svn.freebsd.org>
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Author: cognet Date: Fri Feb 24 18:56:21 2012 New Revision: 232121 URL: http://svn.freebsd.org/changeset/base/232121 Log: Revive those bits, they are needed if uboot isn't there to do the job for us. Modified: projects/armv6/sys/arm/ti/omap4/pandaboard/files.pandaboard projects/armv6/sys/arm/ti/omap4/pandaboard/pandaboard.c Modified: projects/armv6/sys/arm/ti/omap4/pandaboard/files.pandaboard ============================================================================== --- projects/armv6/sys/arm/ti/omap4/pandaboard/files.pandaboard Fri Feb 24 18:39:55 2012 (r232120) +++ projects/armv6/sys/arm/ti/omap4/pandaboard/files.pandaboard Fri Feb 24 18:56:21 2012 (r232121) @@ -1,3 +1,3 @@ # $FreeBSD$ -# arm/ti/omap4/pandaboard/pandaboard.c standard +arm/ti/omap4/pandaboard/pandaboard.c standard Modified: projects/armv6/sys/arm/ti/omap4/pandaboard/pandaboard.c ============================================================================== --- projects/armv6/sys/arm/ti/omap4/pandaboard/pandaboard.c Fri Feb 24 18:39:55 2012 (r232120) +++ projects/armv6/sys/arm/ti/omap4/pandaboard/pandaboard.c Fri Feb 24 18:56:21 2012 (r232121) @@ -41,30 +41,30 @@ __FBSDID("$FreeBSD$"); #include <machine/pte.h> #include <machine/pmap.h> #include <machine/vmparam.h> +#include <machine/fdt.h> -#include <arm/ti/omapvar.h> #include <arm/ti/omap4/omap4var.h> #include <arm/ti/omap4/omap4_reg.h> /* Registers in the SCRM that control the AUX clocks */ -#define SCRM_ALTCLKSRC (OMAP44XX_SCRM_VBASE + 0x110) -#define SCRM_AUXCLK0 (OMAP44XX_SCRM_VBASE + 0x0310) -#define SCRM_AUXCLK1 (OMAP44XX_SCRM_VBASE + 0x0314) -#define SCRM_AUXCLK2 (OMAP44XX_SCRM_VBASE + 0x0318) -#define SCRM_AUXCLK3 (OMAP44XX_SCRM_VBASE + 0x031C) +#define SCRM_ALTCLKSRC (0x110) +#define SCRM_AUXCLK0 (0x0310) +#define SCRM_AUXCLK1 (0x0314) +#define SCRM_AUXCLK2 (0x0318) +#define SCRM_AUXCLK3 (0x031C) /* Some of the GPIO register set */ -#define GPIO1_OE (OMAP44XX_GPIO1_VBASE + 0x0134) -#define GPIO1_CLEARDATAOUT (OMAP44XX_GPIO1_VBASE + 0x0190) -#define GPIO1_SETDATAOUT (OMAP44XX_GPIO1_VBASE + 0x0194) -#define GPIO2_OE (OMAP44XX_GPIO2_VBASE + 0x0134) -#define GPIO2_CLEARDATAOUT (OMAP44XX_GPIO2_VBASE + 0x0190) -#define GPIO2_SETDATAOUT (OMAP44XX_GPIO2_VBASE + 0x0194) +#define GPIO1_OE (0x0134) +#define GPIO1_CLEARDATAOUT (0x0190) +#define GPIO1_SETDATAOUT (0x0194) +#define GPIO2_OE (0x0134) +#define GPIO2_CLEARDATAOUT (0x0190) +#define GPIO2_SETDATAOUT (0x0194) /* Some of the PADCONF register set */ -#define CONTROL_WKUP_PAD0_FREF_CLK3_OUT (OMAP44XX_SCM_PADCONF_VBASE + 0x058) -#define CONTROL_CORE_PAD1_KPD_COL2 (OMAP44XX_SCM_PADCONF_VBASE + 0x186) -#define CONTROL_CORE_PAD0_GPMC_WAIT1 (OMAP44XX_SCM_PADCONF_VBASE + 0x08C) +#define CONTROL_WKUP_PAD0_FREF_CLK3_OUT (0x058) +#define CONTROL_CORE_PAD1_KPD_COL2 (0x186) +#define CONTROL_CORE_PAD0_GPMC_WAIT1 (0x08C) #define REG_WRITE32(r, x) *((volatile uint32_t*)(r)) = (uint32_t)(x) #define REG_READ32(r) *((volatile uint32_t*)(r)) @@ -117,44 +117,60 @@ __FBSDID("$FreeBSD$"); static void usb_hub_init(void) { + bus_space_handle_t scrm_addr, gpio1_addr, gpio2_addr, scm_addr; + if (bus_space_map(fdtbus_bs_tag, OMAP44XX_SCRM_HWBASE, + OMAP44XX_SCRM_SIZE, 0, &scrm_addr) != 0) + panic("Couldn't map SCRM registers"); + if (bus_space_map(fdtbus_bs_tag, OMAP44XX_GPIO1_HWBASE, + OMAP44XX_GPIO1_SIZE, 0, &gpio1_addr) != 0) + panic("Couldn't map GPIO1 registers"); + if (bus_space_map(fdtbus_bs_tag, OMAP44XX_GPIO2_HWBASE, + OMAP44XX_GPIO2_SIZE, 0, &gpio2_addr) != 0) + panic("Couldn't map GPIO2 registers"); + if (bus_space_map(fdtbus_bs_tag, OMAP44XX_SCM_PADCONF_HWBASE, + OMAP44XX_SCM_PADCONF_SIZE, 0, &scm_addr) != 0) + panic("Couldn't map SCM Padconf registers"); + + /* Need to set FREF_CLK3_OUT to 19.2 MHz and pump it out on pin GPIO_WK31. * We know the SYS_CLK is 38.4Mhz and therefore to get the needed 19.2Mhz, * just use a 2x divider and ensure the SYS_CLK is used as the source. */ - //int pouet = REG_READ32(SCRM_AUXCLK3); - REG_WRITE32(SCRM_AUXCLK3, (1 << 16) | /* Divider of 2 */ + REG_WRITE32(scrm_addr + SCRM_AUXCLK3, (1 << 16) | /* Divider of 2 */ (0 << 1) | /* Use the SYS_CLK as the source */ (1 << 8)); /* Enable the clock */ -#if 0 - REG_WRITE32(SCRM_ALTCLKSRC, (1 << 1) | ( 3 << 2)); -#endif /* Enable the clock out to the pin (GPIO_WK31). * muxmode=fref_clk3_out, pullup/down=disabled, input buffer=disabled, * wakeup=disabled. */ - REG_WRITE16(CONTROL_WKUP_PAD0_FREF_CLK3_OUT, 0x0000); + REG_WRITE16(scm_addr + CONTROL_WKUP_PAD0_FREF_CLK3_OUT, 0x0000); /* Disable the power to the USB hub, drive GPIO1 low */ - REG_WRITE32(GPIO1_OE, REG_READ32(GPIO1_OE) & ~(1UL << 1)); - REG_WRITE32(GPIO1_CLEARDATAOUT, (1UL << 1)); - REG_WRITE16(CONTROL_CORE_PAD1_KPD_COL2, 0x0003); + REG_WRITE32(gpio1_addr + GPIO1_OE, REG_READ32(gpio1_addr + + GPIO1_OE) & ~(1UL << 1)); + REG_WRITE32(gpio1_addr + GPIO1_CLEARDATAOUT, (1UL << 1)); + REG_WRITE16(scm_addr + CONTROL_CORE_PAD1_KPD_COL2, 0x0003); /* Reset the USB PHY and Hub using GPIO_62 */ - REG_WRITE32(GPIO2_OE, REG_READ32(GPIO2_OE) & ~(1UL << 30)); - REG_WRITE32(GPIO2_CLEARDATAOUT, (1UL << 30)); - REG_WRITE16(CONTROL_CORE_PAD0_GPMC_WAIT1, 0x0003); + REG_WRITE32(gpio2_addr + GPIO2_OE, + REG_READ32(gpio2_addr + GPIO2_OE) & ~(1UL << 30)); + REG_WRITE32(gpio2_addr + GPIO2_CLEARDATAOUT, (1UL << 30)); + REG_WRITE16(scm_addr + CONTROL_CORE_PAD0_GPMC_WAIT1, 0x0003); DELAY(10); - REG_WRITE32(GPIO2_SETDATAOUT, (1UL << 30)); + REG_WRITE32(gpio2_addr + GPIO2_SETDATAOUT, (1UL << 30)); /* Enable power to the hub (GPIO_1) */ - REG_WRITE32(GPIO1_SETDATAOUT, (1UL << 1)); - + REG_WRITE32(gpio1_addr + GPIO1_SETDATAOUT, (1UL << 1)); + bus_space_unmap(fdtbus_bs_tag, scrm_addr, OMAP44XX_SCRM_SIZE); + bus_space_unmap(fdtbus_bs_tag, gpio1_addr, OMAP44XX_GPIO1_SIZE); + bus_space_unmap(fdtbus_bs_tag, gpio2_addr, OMAP44XX_GPIO2_SIZE); + bus_space_unmap(fdtbus_bs_tag, scm_addr, OMAP44XX_SCM_PADCONF_SIZE); } /**
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