Date: Tue, 28 Feb 2017 14:02:16 +0000 (UTC) From: Ruslan Bukin <br@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r314389 - in head/sys: arm/altera/socfpga arm/conf boot/fdt/dts/arm Message-ID: <201702281402.v1SE2GRw072657@repo.freebsd.org>
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Author: br Date: Tue Feb 28 14:02:16 2017 New Revision: 314389 URL: https://svnweb.freebsd.org/changeset/base/314389 Log: Add support for Intel Arria 10 SoC Development Kit. Use standard DTS files for SOCKIT and SOCDK. Sponsored by: DARPA, AFRL Added: head/sys/arm/conf/SOCDK (contents, props changed) head/sys/arm/conf/SOCFPGA (contents, props changed) head/sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts (contents, props changed) head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts (contents, props changed) head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts (contents, props changed) Deleted: head/sys/arm/conf/SOCKIT.common head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts head/sys/boot/fdt/dts/arm/socfpga-sockit.dts head/sys/boot/fdt/dts/arm/socfpga.dtsi Modified: head/sys/arm/altera/socfpga/socfpga_machdep.c head/sys/arm/altera/socfpga/socfpga_manager.c head/sys/arm/altera/socfpga/socfpga_mp.c head/sys/arm/altera/socfpga/socfpga_mp.h head/sys/arm/altera/socfpga/socfpga_rstmgr.c head/sys/arm/altera/socfpga/socfpga_rstmgr.h head/sys/arm/conf/SOCKIT head/sys/arm/conf/SOCKIT-BERI Modified: head/sys/arm/altera/socfpga/socfpga_machdep.c ============================================================================== --- head/sys/arm/altera/socfpga/socfpga_machdep.c Tue Feb 28 12:05:58 2017 (r314388) +++ head/sys/arm/altera/socfpga/socfpga_machdep.c Tue Feb 28 14:02:16 2017 (r314389) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> + * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com> * All rights reserved. * * This software was developed by SRI International and the University of @@ -83,24 +83,43 @@ socfpga_devmap_init(platform_t plat) return (0); } +static int +socfpga_a10_devmap_init(platform_t plat) +{ + + /* UART */ + devmap_add_entry(0xffc00000, 0x100000); + + /* USB OTG */ + devmap_add_entry(0xffb00000, 0x100000); + + /* dwmmc */ + devmap_add_entry(0xff800000, 0x100000); + + /* scu */ + devmap_add_entry(0xfff00000, 0x100000); + + return (0); +} + static void -socfpga_cpu_reset(platform_t plat) +_socfpga_cpu_reset(platform_t plat, uint32_t reg) { uint32_t paddr; bus_addr_t vaddr; phandle_t node; - if (rstmgr_warmreset() == 0) + if (rstmgr_warmreset(reg) == 0) goto end; - node = OF_finddevice("rstmgr"); + node = OF_finddevice("/soc/rstmgr"); if (node == -1) goto end; if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) { if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) { bus_space_write_4(fdtbus_bs_tag, vaddr, - RSTMGR_CTRL, CTRL_SWWARMRSTREQ); + reg, CTRL_SWWARMRSTREQ); } } @@ -108,16 +127,38 @@ end: while (1); } +static void +socfpga_cpu_reset(platform_t plat) +{ + + _socfpga_cpu_reset(plat, RSTMGR_CTRL); +} + +static void +socfpga_a10_cpu_reset(platform_t plat) +{ + + _socfpga_cpu_reset(plat, RSTMGR_A10_CTRL); +} + static platform_method_t socfpga_methods[] = { PLATFORMMETHOD(platform_devmap_init, socfpga_devmap_init), PLATFORMMETHOD(platform_cpu_reset, socfpga_cpu_reset), - #ifdef SMP PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid), PLATFORMMETHOD(platform_mp_start_ap, socfpga_mp_start_ap), #endif - PLATFORMMETHOD_END, }; +FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5", 200); -FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga", 0); +static platform_method_t socfpga_a10_methods[] = { + PLATFORMMETHOD(platform_devmap_init, socfpga_a10_devmap_init), + PLATFORMMETHOD(platform_cpu_reset, socfpga_a10_cpu_reset), +#ifdef SMP + PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid), + PLATFORMMETHOD(platform_mp_start_ap, socfpga_a10_mp_start_ap), +#endif + PLATFORMMETHOD_END, +}; +FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10", 200); Modified: head/sys/arm/altera/socfpga/socfpga_manager.c ============================================================================== --- head/sys/arm/altera/socfpga/socfpga_manager.c Tue Feb 28 12:05:58 2017 (r314388) +++ head/sys/arm/altera/socfpga/socfpga_manager.c Tue Feb 28 14:02:16 2017 (r314389) @@ -377,7 +377,7 @@ fpgamgr_probe(device_t dev) if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "altr,fpga-mgr")) + if (!ofw_bus_is_compatible(dev, "altr,socfpga-fpga-mgr")) return (ENXIO); device_set_desc(dev, "FPGA Manager"); Modified: head/sys/arm/altera/socfpga/socfpga_mp.c ============================================================================== --- head/sys/arm/altera/socfpga/socfpga_mp.c Tue Feb 28 12:05:58 2017 (r314388) +++ head/sys/arm/altera/socfpga/socfpga_mp.c Tue Feb 28 14:02:16 2017 (r314389) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> + * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com> * All rights reserved. * * This software was developed by SRI International and the University of @@ -50,8 +50,10 @@ __FBSDID("$FreeBSD$"); #include <machine/platformvar.h> #include <arm/altera/socfpga/socfpga_mp.h> +#include <arm/altera/socfpga/socfpga_rstmgr.h> #define SCU_PHYSBASE 0xFFFEC000 +#define SCU_PHYSBASE_A10 0xFFFFC000 #define SCU_SIZE 0x100 #define SCU_CONTROL_REG 0x00 @@ -69,11 +71,12 @@ __FBSDID("$FreeBSD$"); #define RSTMGR_PHYSBASE 0xFFD05000 #define RSTMGR_SIZE 0x100 -#define MPUMODRST 0x10 -#define MPUMODRST_CPU1 (1 << 1) #define RAM_PHYSBASE 0x0 -#define RAM_SIZE 0x1000 +#define RAM_SIZE 0x1000 + +#define SOCFPGA_SOCKIT 1 +#define SOCFPGA_SOCDK 2 extern char *mpentry_addr; static void socfpga_trampoline(void); @@ -109,15 +112,22 @@ socfpga_mp_setmaxid(platform_t plat) mp_maxid = ncpu - 1; } -void -socfpga_mp_start_ap(platform_t plat) + +static void +_socfpga_mp_start_ap(platform_t plat, uint32_t platid) { bus_space_handle_t scu, rst, ram; int reg; - if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, - SCU_SIZE, 0, &scu) != 0) + if (platid == SOCFPGA_SOCDK) { + if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10, + SCU_SIZE, 0, &scu) != 0) panic("Couldn't map the SCU\n"); + } else { + if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, + SCU_SIZE, 0, &scu) != 0) + panic("Couldn't map the SCU\n"); + } if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE, RSTMGR_SIZE, 0, &rst) != 0) panic("Couldn't map the reset manager (RSTMGR)\n"); @@ -139,7 +149,13 @@ socfpga_mp_start_ap(platform_t plat) bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg); /* Put CPU1 to reset state */ - bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, MPUMODRST_CPU1); + if (platid == SOCFPGA_SOCDK) { + bus_space_write_4(fdtbus_bs_tag, rst, + RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1); + } else { + bus_space_write_4(fdtbus_bs_tag, rst, + RSTMGR_MPUMODRST, MPUMODRST_CPU1); + } /* Enable the SCU, then clean the cache on this core */ reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); @@ -154,7 +170,13 @@ socfpga_mp_start_ap(platform_t plat) dcache_wbinv_poc_all(); /* Put CPU1 out from reset */ - bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0); + if (platid == SOCFPGA_SOCDK) { + bus_space_write_4(fdtbus_bs_tag, rst, + RSTMGR_A10_MPUMODRST, 0); + } else { + bus_space_write_4(fdtbus_bs_tag, rst, + RSTMGR_MPUMODRST, 0); + } dsb(); sev(); @@ -163,3 +185,18 @@ socfpga_mp_start_ap(platform_t plat) bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE); bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE); } + +void +socfpga_a10_mp_start_ap(platform_t plat) +{ + + _socfpga_mp_start_ap(plat, SOCFPGA_SOCDK); +} + +void +socfpga_mp_start_ap(platform_t plat) +{ + + _socfpga_mp_start_ap(plat, SOCFPGA_SOCKIT); +} + Modified: head/sys/arm/altera/socfpga/socfpga_mp.h ============================================================================== --- head/sys/arm/altera/socfpga/socfpga_mp.h Tue Feb 28 12:05:58 2017 (r314388) +++ head/sys/arm/altera/socfpga/socfpga_mp.h Tue Feb 28 14:02:16 2017 (r314389) @@ -30,5 +30,6 @@ void socfpga_mp_setmaxid(platform_t); void socfpga_mp_start_ap(platform_t); +void socfpga_a10_mp_start_ap(platform_t); #endif /* _SOCFPGA_MP_H_ */ Modified: head/sys/arm/altera/socfpga/socfpga_rstmgr.c ============================================================================== --- head/sys/arm/altera/socfpga/socfpga_rstmgr.c Tue Feb 28 12:05:58 2017 (r314388) +++ head/sys/arm/altera/socfpga/socfpga_rstmgr.c Tue Feb 28 14:02:16 2017 (r314389) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> + * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com> * All rights reserved. * * This software was developed by SRI International and the University of @@ -166,7 +166,7 @@ rstmgr_sysctl(SYSCTL_HANDLER_ARGS) } int -rstmgr_warmreset(void) +rstmgr_warmreset(uint32_t reg) { struct rstmgr_softc *sc; @@ -175,8 +175,7 @@ rstmgr_warmreset(void) return (1); /* Request warm reset */ - WRITE4(sc, RSTMGR_CTRL, - CTRL_SWWARMRSTREQ); + WRITE4(sc, reg, CTRL_SWWARMRSTREQ); return (0); } @@ -214,6 +213,7 @@ rstmgr_probe(device_t dev) return (ENXIO); device_set_desc(dev, "Reset Manager"); + return (BUS_PROBE_DEFAULT); } Modified: head/sys/arm/altera/socfpga/socfpga_rstmgr.h ============================================================================== --- head/sys/arm/altera/socfpga/socfpga_rstmgr.h Tue Feb 28 12:05:58 2017 (r314388) +++ head/sys/arm/altera/socfpga/socfpga_rstmgr.h Tue Feb 28 14:02:16 2017 (r314389) @@ -35,6 +35,7 @@ #define CTRL_SWWARMRSTREQ (1 << 1) /* Trigger warm reset */ #define RSTMGR_COUNTS 0x8 /* Reset Cycles Count */ #define RSTMGR_MPUMODRST 0x10 /* MPU Module Reset */ +#define MPUMODRST_CPU1 (1 << 1) #define RSTMGR_PERMODRST 0x14 /* Peripheral Module Reset */ #define RSTMGR_PER2MODRST 0x18 /* Peripheral 2 Module Reset */ #define RSTMGR_BRGMODRST 0x1C /* Bridge Module Reset */ @@ -43,4 +44,7 @@ #define BRGMODRST_HPS2FPGA (1 << 0) #define RSTMGR_MISCMODRST 0x20 /* Miscellaneous Module Reset */ -int rstmgr_warmreset(void); +#define RSTMGR_A10_CTRL 0xC /* Control */ +#define RSTMGR_A10_MPUMODRST 0x20 /* MPU Module Reset */ + +int rstmgr_warmreset(uint32_t reg); Added: head/sys/arm/conf/SOCDK ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/arm/conf/SOCDK Tue Feb 28 14:02:16 2017 (r314389) @@ -0,0 +1,30 @@ +# +# Kernel configuration for Altera Arria10 SOC Development Kit. +# +# For more information on this file, please read the config(5) manual page, +# and/or the handbook section on Kernel Configuration Files: +# +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html +# +# The handbook is also available locally in /usr/share/doc/handbook +# if you've installed the doc distribution, otherwise always see the +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the +# latest information. +# +# An exhaustive list of options and more detailed explanations of the +# device lines is also present in the ../../conf/NOTES and NOTES files. +# If you are in doubt as to the purpose or necessity of a line, check first +# in NOTES. +# +# $FreeBSD$ + +#NO_UNIVERSE + +include "SOCFPGA" +ident SOCDK + +options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\" + +# Flattened Device Tree +options FDT_DTB_STATIC +makeoptions FDT_DTS_FILE=socfpga_arria10_socdk_sdmmc.dts Added: head/sys/arm/conf/SOCFPGA ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/arm/conf/SOCFPGA Tue Feb 28 14:02:16 2017 (r314389) @@ -0,0 +1,97 @@ +# +# Kernel configuration for Altera SOCFPGA development kits. +# +# For more information on this file, please read the config(5) manual page, +# and/or the handbook section on Kernel Configuration Files: +# +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html +# +# The handbook is also available locally in /usr/share/doc/handbook +# if you've installed the doc distribution, otherwise always see the +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the +# latest information. +# +# An exhaustive list of options and more detailed explanations of the +# device lines is also present in the ../../conf/NOTES and NOTES files. +# If you are in doubt as to the purpose or necessity of a line, check first +# in NOTES. +# +# $FreeBSD$ + +ident SOCFPGA +include "std.armv6" +include "../altera/socfpga/std.socfpga" + +makeoptions MODULES_OVERRIDE="" + +makeoptions WERROR="-Werror" + +options SCHED_ULE # ULE scheduler +options PLATFORM # Platform based SoC +options PLATFORM_SMP +options SMP # Enable multiple cores +options MULTIDELAY + +# NFS root from boopt/dhcp +#options BOOTP +#options BOOTP_NFSROOT +#options BOOTP_COMPAT +#options BOOTP_NFSV3 +#options BOOTP_WIRED_TO=ue0 + +# Interrupt controller +device gic +options INTRNG + +# ARM MPCore timer +device mpcore_timer + +# MMC/SD/SDIO Card slot support +device mmc # mmc/sd bus +device mmcsd # mmc/sd flash cards +device dwmmc + +# Pseudo devices + +device loop +device random +device pty +device md +device gpio + +# USB support +options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. +device usb +device dwcotg + +device umass +device scbus # SCSI bus (required for ATA/SCSI) +device da # Direct Access (disks) +device pass + +# Serial ports +device uart +device uart_snps + +# I2C (TWSI) +device iic +device iicbus + +# SPI +device spibus + +# Ethernet +device ether +device mii +device smsc +device smscphy +device dwc +device micphy + +# USB ethernet support, requires miibus +device miibus +device axe # ASIX Electronics USB Ethernet +device bpf # Berkeley packet filter + +# Flattened Device Tree +options FDT # Configure using FDT/DTB data Modified: head/sys/arm/conf/SOCKIT ============================================================================== --- head/sys/arm/conf/SOCKIT Tue Feb 28 12:05:58 2017 (r314388) +++ head/sys/arm/conf/SOCKIT Tue Feb 28 14:02:16 2017 (r314389) @@ -20,11 +20,11 @@ #NO_UNIVERSE +include "SOCFPGA" ident SOCKIT -include "SOCKIT.common" -options ROOTDEVNAME=\"ufs:/dev/da0\" +options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\" # Flattened Device Tree options FDT_DTB_STATIC -makeoptions FDT_DTS_FILE=socfpga-sockit.dts +makeoptions FDT_DTS_FILE=socfpga_cyclone5_sockit_sdmmc.dts Modified: head/sys/arm/conf/SOCKIT-BERI ============================================================================== --- head/sys/arm/conf/SOCKIT-BERI Tue Feb 28 12:05:58 2017 (r314388) +++ head/sys/arm/conf/SOCKIT-BERI Tue Feb 28 14:02:16 2017 (r314389) @@ -18,8 +18,10 @@ # # $FreeBSD$ +#NO_UNIVERSE + +include "SOCFPGA" ident SOCKIT-BERI -include "SOCKIT.common" options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\" @@ -32,4 +34,4 @@ device altera_pio # Flattened Device Tree options FDT_DTB_STATIC -makeoptions FDT_DTS_FILE=socfpga-sockit-beri.dts +makeoptions FDT_DTS_FILE=socfpga_cyclone5_sockit_beri_sdmmc.dts Added: head/sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts Tue Feb 28 14:02:16 2017 (r314389) @@ -0,0 +1,82 @@ +/*- + * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com> + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +/ { + model = "Altera SOCFPGA Arria 10"; + compatible = "altr,socfpga-arria10", "altr,socfpga"; + + /* Reserve first page for secondary CPU trampoline code */ + memreserve = < 0x00000000 0x1000 >; + + soc { + /* Local timer */ + timer@ffffc600 { + clock-frequency = <200000000>; + }; + + /* Global timer */ + global_timer: timer@ffffc200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xffffc200 0x20>; + interrupts = <1 11 0x301>; + clock-frequency = <200000000>; + }; + }; + + chosen { + stdin = "serial1"; + stdout = "serial1"; + }; +}; + +&uart1 { + clock-frequency = < 50000000 >; +}; + +&mmc { + status = "okay"; + num-slots = <1>; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; + bus-frequency = <200000000>; +}; + +&i2c1 { + lcd@28 { + compatible = "newhaven,nhd-0216k3z-nsw-bbw"; + reg = <0x28>; + }; +}; Added: head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts Tue Feb 28 14:02:16 2017 (r314389) @@ -0,0 +1,153 @@ +/*- + * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com> + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* /dts-v1/; */ +#include "socfpga_cyclone5_sockit.dts" + +/ { + model = "Terasic SoCkit"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */ + < 0x00001000 0x1000 >, /* virtio block */ + < 0x00002000 0x1000 >; /* virtio net */ + + soc { + /* Local timer */ + timer@fffec600 { + clock-frequency = <200000000>; + }; + + /* Global timer */ + global_timer: timer@fffec200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xfffec200 0x20>; + interrupts = <1 11 0xf04>; + clock-frequency = <200000000>; + }; + + beri_mem0: mem@d0000000 { + compatible = "sri-cambridge,beri-mem"; + reg = <0xd0000000 0x10000000>; /* 256mb */ + status = "okay"; + }; + + pio0: pio@c0020000 { + compatible = "altr,pio"; + reg = <0xc0020000 0x1000>; /* recv */ + interrupts = < 76 >; + status = "okay"; + }; + + pio1: pio@c0021000 { + compatible = "altr,pio"; + reg = <0xc0021000 0x1000>; /* send */ + interrupts = < 82 >; /* not in use on arm side */ + status = "okay"; + }; + + pio2: pio@c0022000 { + compatible = "altr,pio"; + reg = <0xc0022000 0x1000>; /* recv */ + interrupts = < 77 >; + status = "okay"; + }; + + pio3: pio@c0023000 { + compatible = "altr,pio"; + reg = <0xc0023000 0x1000>; /* send */ + interrupts = < 83 >; /* not in use on arm side */ + status = "okay"; + }; + + beri_vtblk: vtblk@00001000 { + compatible = "sri-cambridge,beri-vtblk"; + reg = <0x00001000 0x1000>; + pio-recv = <&pio0>; + pio-send = <&pio1>; + beri-mem = <&beri_mem0>; + status = "okay"; + }; + + beri_vtnet: vtnet@00002000 { + compatible = "sri-cambridge,beri-vtnet"; + reg = <0x00002000 0x1000>; + pio-recv = <&pio2>; + pio-send = <&pio3>; + beri-mem = <&beri_mem0>; + status = "okay"; + }; + + beri_debug: ring@c0000000 { + compatible = "sri-cambridge,beri-ring"; + reg = <0xc0000000 0x3000>; + interrupts = < 72 73 >; + device_name = "beri_debug"; + data_size = <0x1000>; + data_read = <0x0>; + data_write = <0x1000>; + control_read = <0x2000>; + control_write = <0x2010>; + status = "okay"; + }; + + beri_console: ring@c0004000 { + compatible = "sri-cambridge,beri-ring"; + reg = <0xc0004000 0x3000>; + interrupts = < 74 75 >; + device_name = "beri_console"; + data_size = <0x1000>; + data_read = <0x0>; + data_write = <0x1000>; + control_read = <0x2000>; + control_write = <0x2010>; + status = "okay"; + }; + }; + + chosen { + stdin = "serial0"; + stdout = "serial0"; + }; +}; + +&mmc0 { + bus-frequency = <25000000>; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&uart1 { + status = "disabled"; +}; Added: head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts Tue Feb 28 14:02:16 2017 (r314389) @@ -0,0 +1,74 @@ +/*- + * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com> + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* /dts-v1/; */ +#include "socfpga_cyclone5_sockit.dts" + +/ { + model = "Terasic SoCkit"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + /* Reserve first page for secondary CPU trampoline code */ + memreserve = < 0x00000000 0x1000 >; + + soc { + /* Local timer */ + timer@fffec600 { + clock-frequency = <200000000>; + }; + + /* Global timer */ + global_timer: timer@fffec200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xfffec200 0x20>; + interrupts = <1 11 0xf04>; + clock-frequency = <200000000>; + }; + }; + + chosen { + stdin = "serial0"; + stdout = "serial0"; + }; +}; + +&mmc0 { + bus-frequency = <25000000>; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&uart1 { + status = "disabled"; +};
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