Date: Sun, 25 Oct 2009 21:25:41 +0100 From: Marius Strobl <marius@alchemy.franken.de> To: Marcel Moolenaar <marcel@freebsd.org> Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org Subject: Re: svn commit: r198341 - in head/sys: amd64/amd64 arm/arm arm/mv i386/i386 i386/xen ia64/ia64 kern mips/mips powerpc/aim powerpc/booke powerpc/include powerpc/powerpc sparc64/sparc64 sun4v/sun4v vm Message-ID: <20091025202541.GC94979@alchemy.franken.de> In-Reply-To: <200910211838.n9LIc2wp007206@svn.freebsd.org> References: <200910211838.n9LIc2wp007206@svn.freebsd.org>
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On Wed, Oct 21, 2009 at 06:38:02PM +0000, Marcel Moolenaar wrote: > Author: marcel > Date: Wed Oct 21 18:38:02 2009 > New Revision: 198341 > URL: http://svn.freebsd.org/changeset/base/198341 > > Log: > o Introduce vm_sync_icache() for making the I-cache coherent with > the memory or D-cache, depending on the semantics of the platform. > vm_sync_icache() is basically a wrapper around pmap_sync_icache(), > that translates the vm_map_t argumument to pmap_t. > o Introduce pmap_sync_icache() to all PMAP implementation. For powerpc > it replaces the pmap_page_executable() function, added to solve > the I-cache problem in uiomove_fromphys(). > o In proc_rwmem() call vm_sync_icache() when writing to a page that > has execute permissions. This assures that when breakpoints are > written, the I-cache will be coherent and the process will actually > hit the breakpoint. > o This also fixes the Book-E PMAP implementation that was missing > necessary locking while trying to deal with the I-cache coherency > in pmap_enter() (read: mmu_booke_enter_locked). > > The key property of this change is that the I-cache is made coherent > *after* writes have been done. Doing it in the PMAP layer when adding > or changing a mapping means that the I-cache is made coherent *before* > any writes happen. The difference is key when the I-cache prefetches. > Do you have a simple test case demonstrating the need for I-cache synchronisation? Marius
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