Date: Tue, 21 Mar 1995 22:17:38 -0800 (PST) From: Poul-Henning Kamp <phk@ref.tfs.com> To: bde@zeta.org.au (Bruce Evans) Cc: davidg@freefall.cdrom.com, rgrimes@gndrsh.aac.dev.com, CVS-commiters@freefall.cdrom.com, cvs-sys@freefall.cdrom.com Subject: Re: cvs commit: src/sys/i386/isa wd.c wdreg.h Message-ID: <199503220617.WAA04027@ref.tfs.com> In-Reply-To: <199503220610.QAA04588@godzilla.zeta.org.au> from "Bruce Evans" at Mar 22, 95 04:10:18 pm
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> >Port 0x84 will not cause the 1.25uS delay on some PCI motherboards,
> >I beleive all Intel Neptune and Triton based boards know that this
> >is not an ISA address and end up running only a PCI I/O cycle for
> >it.
Couldn't we just make a spin for a number of updates to the 1.19MHz
counter (#2 ?) for this kind of delays ? For 1.25 uS we want to
see it change twice:
n=2;
a= inb(TIMER);
while (n--) {
while (a == (b = inb(TIMER)))
;
a = b;
}
Wouldn't that be a sensible addition to DELAY (microDELAY ?)
--
Poul-Henning Kamp <phk@login.dknet.dk> -- TRW Financial Systems, Inc.
'All relevant people are pertinent' && 'All rude people are impertinent'
=> 'no rude people are relevant'
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