Date: Thu, 30 Jul 2009 17:51:51 -0700 (PDT) From: Neelkanth Natu <neelnatu@yahoo.com> To: freebsd-mips@freebsd.org Subject: Diffs to fix L1 cache flush problems Message-ID: <153254.15259.qm@web34402.mail.mud.yahoo.com>
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Hi,
This is a simple change that fixes problems invalidating L1
data/instruction caches. The problem is that the type of the variable
that holds the size of the instruction/data caches is uint8_t. Clearly
this is going to overflow.
On the Sibyte with 32KB cache size the uint8_t was causing it to be
truncated to 0. This in turn makes the cache flush routines turn into
no-ops.
I ran into this when testing kernel loadable modules and have verified that
this change fixes the problem.
best
Neel
==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/include/cpuinfo.h#2 (text) - //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/include/cpuinfo.h#3 (text) ==== content
@@ -57,11 +57,11 @@
u_int16_t tlb_nentries;
u_int8_t icache_virtual;
struct {
- u_int8_t ic_size;
+ unsigned int ic_size;
u_int8_t ic_linesize;
u_int8_t ic_nways;
u_int16_t ic_nsets;
- u_int8_t dc_size;
+ unsigned int dc_size;
u_int8_t dc_linesize;
u_int8_t dc_nways;
u_int16_t dc_nsets;
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