Date: Thu, 13 Mar 2003 11:17:49 -0500 (EST) From: John Baldwin <jhb@FreeBSD.org> To: "Mike O'Brien" <obrien@leonardo.net> Cc: freebsd-smp@freebsd.org Subject: Re: Question about number of CPUs Message-ID: <XFMail.20030313111749.jhb@FreeBSD.org> In-Reply-To: <200303130914.h2D9ECq00356@c-24-130-253-104.we.client2.attbi.com>
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On 13-Mar-2003 Mike O'Brien wrote:
> Here is the output of acpidump on that machine. It does list four
> CPUs, but I can't tell from this table which APIC IDs are associated with
> which physical processors. The two processors that are detected have
> APIC IDs of 0 and 1. If these are separate processors, I figure I should
> just wait for the correct APIC code to appear, since hyperthreading will
> only improve performance by about 30%, if I remember correctly. But if
> these are two cores on the same physical processor then I'm planning to
> crash around in mp_machdep.c and do whatever I have to do to get the
> second physical processor on this particular machine to show up.
Humm, it does seem that your BIOS is broken and is reporting the two cores
on CPU 0 in the mptable. :-/ The part at the end here lists the 4 cpus
and their APIC IDs as 0, 1, 2, and 3. According to the IA-32 docs I've
read, when HTT is used, the APIC ID's of logical cores within a physical
CPU are consecutive, i.e. x then x+1.
> /*
> APIC: Length=156, Revision=1, Checksum=90,
> OEMID=IntelR, OEM Table ID=AWRDACPI, OEM Revision=0x42302e31,
> Creator ID=AWRD, Creator Revision=0x0
> */
> /*
> Local APIC ADDR=0xfee00000
> Flags={PC-AT}
This tells us the physical address that the local APIC resides at. Well
the address that it decodes and that this system has a PC-AT compat mode
meaning it has 8259A's that can do interrupts.
> Type=Local APIC
> ACPI CPU=0
> Flags={ENABLED}
> APIC ID=0
>
> Type=Local APIC
> ACPI CPU=1
> Flags={ENABLED}
> APIC ID=1
>
> Type=Local APIC
> ACPI CPU=2
> Flags={ENABLED}
> APIC ID=2
>
> Type=Local APIC
> ACPI CPU=3
> Flags={ENABLED}
> APIC ID=3
These are your four CPU's with APIC IDs 0, 1, 2, and 3. BTW, if you
disable HTT in your BIOS, then APIC IDs 1 and 3 should become
DISABLED instead of ENABLED. Or rather, they may have a flags of
{}. (Lack of ENABLED)
> Type=IO APIC
> APIC ID=4
> INT BASE=0
> ADDR=0xfec00000
>
> Type=IO APIC
> APIC ID=5
> INT BASE=24
> ADDR=0xfec80000
>
> Type=IO APIC
> APIC ID=6
> INT BASE=48
> ADDR=0xfec80400
These are your IO APICs along with the addresses they decode for
access to their registers and the base global interrupt number for
their interrupt pins. I.e., pin 2 on IO APIC 1 (ID 5) would have
a global interrupt number of 2 + 24 = 26. Part of my ACPI work is
to rework our current APIC code to use a similar global interrupt
number scheme with the mptable and IO APICs and to then fix our
PCI interrupt routing code for mptable SMP.
> Type=INT Override
> BUS=0
> IRQ=0
> INTR=2
> Flags={Polarity=conforming, Trigger=conforming}
>
> Type=INT Override
> BUS=0
> IRQ=9
> INTR=9
> Flags={Polarity=active-hi, Trigger=level}
These are the normal pin overrides on IO APIC 0 (IRQ 0 is
mapped to pin 2 because pin 0 is used for the mixed mode
pass through and the 8259's don't have a real IRQ 2). IRQ
9 mapping to pin 9 seems rather normal except that it is
level triggered instead of edge triggered.
> Type=Local NMI
> ACPI CPU=0
> LINT Pin=1
> Flags={Polarity=active-hi, Trigger=edge}
>
> Type=Local NMI
> ACPI CPU=0
> LINT Pin=1
> Flags={Polarity=active-hi, Trigger=edge}
>
> Type=Local NMI
> ACPI CPU=0
> LINT Pin=1
> Flags={Polarity=active-hi, Trigger=edge}
>
> Type=Local NMI
> ACPI CPU=0
> LINT Pin=1
> Flags={Polarity=active-hi, Trigger=edge}
This says that the local interrupt pin 1 on each CPU
is wired up to an NMI.
> */
--
John Baldwin <jhb@FreeBSD.org> <>< http://www.FreeBSD.org/~jhb/
"Power Users Use the Power to Serve!" - http://www.FreeBSD.org/
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