Date: Mon, 11 Nov 2019 21:59:21 +0000 (UTC) From: Konstantin Belousov <kib@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r354630 - head/sys/amd64/amd64 Message-ID: <201911112159.xABLxLOS054437@repo.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: kib Date: Mon Nov 11 21:59:20 2019 New Revision: 354630 URL: https://svnweb.freebsd.org/changeset/base/354630 Log: amd64: Issue MFENCE on context switch on AMD CPUs when reusing address space. On some AMD CPUs, in particular, machines that do not implement CLFLUSHOPT but do provide CLFLUSH, the CLFLUSH instruction is only synchronized with MFENCE. Code using CLFLUSH typicall needs to brace it with MFENCE both before and after flush, see for instance pmap_invalidate_cache_range(). If context switch occurs while inside the protected region, we need to ensure visibility of flushes done on the old CPU, to new CPU. For all other machines, locked operation done to lock switched thread, should be enough. For case of different address spaces, reload of %cr3 is serializing. Reviewed by: cem, jhb, scottph Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D22007 Modified: head/sys/amd64/amd64/pmap.c Modified: head/sys/amd64/amd64/pmap.c ============================================================================== --- head/sys/amd64/amd64/pmap.c Mon Nov 11 20:44:30 2019 (r354629) +++ head/sys/amd64/amd64/pmap.c Mon Nov 11 21:59:20 2019 (r354630) @@ -8810,8 +8810,11 @@ pmap_activate_sw(struct thread *td) oldpmap = PCPU_GET(curpmap); pmap = vmspace_pmap(td->td_proc->p_vmspace); - if (oldpmap == pmap) + if (oldpmap == pmap) { + if (cpu_vendor_id != CPU_VENDOR_INTEL) + mfence(); return; + } cpuid = PCPU_GET(cpuid); #ifdef SMP CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201911112159.xABLxLOS054437>