Date: Wed, 22 Feb 2006 23:59:12 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 92244 for review Message-ID: <200602222359.k1MNxCWr094486@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=92244 Change 92244 by imp@imp_Speedy on 2006/02/22 23:59:07 Table driven device list. This will allow us to port to other members of the AT91 family that are ARM9 a little more easily. Affected files ... .. //depot/projects/arm/src/sys/arm/at91/at91.c#11 edit .. //depot/projects/arm/src/sys/arm/at91/at91rm92reg.h#16 edit Differences ... ==== //depot/projects/arm/src/sys/arm/at91/at91.c#11 (text+ko) ==== @@ -195,7 +195,7 @@ static void at91_add_child(device_t dev, int prio, const char *name, int unit, - bus_addr_t addr, bus_size_t size, int irq) + bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2) { device_t kid; struct at91_ivar *ivar; @@ -210,12 +210,175 @@ } device_set_ivars(kid, ivar); resource_list_init(&ivar->resources); - if (irq != -1) - bus_set_resource(kid, SYS_RES_IRQ, 0, irq, 1); + if (irq0 != -1) + bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1); + if (irq1 != 0) + bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1); + if (irq2 != 0) + bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1); if (addr != 0) bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size); } +struct cpu_devs +{ + const char *name; + int unit; + bus_addr_t mem_base; + bus_size_t mem_len; + int irq0; + int irq1; + int irq2; +}; + +struct cpu_devs at91rm9200_devs[] = +{ + // All the "system" devices + { + "at91_st", 0, + AT91RM92_BASE + AT91RM92_ST_BASE, AT91RM92_ST_SIZE, + AT91RM92_IRQ_SYSTEM + }, + { + "at91_pio", 0, + AT91RM92_BASE + AT91RM92_PIOA_BASE, AT91RM92_PIO_SIZE, + AT91RM92_IRQ_SYSTEM + }, + { + "at91_pio", 1, + AT91RM92_BASE + AT91RM92_PIOB_BASE, AT91RM92_PIO_SIZE, + AT91RM92_IRQ_SYSTEM + }, + { + "at91_pio", 2, + AT91RM92_BASE + AT91RM92_PIOC_BASE, AT91RM92_PIO_SIZE, + AT91RM92_IRQ_SYSTEM + }, + { + "at91_pio", 3, + AT91RM92_BASE + AT91RM92_PIOD_BASE, AT91RM92_PIO_SIZE, + AT91RM92_IRQ_SYSTEM + }, + { + "at91_pmc", 0, + AT91RM92_BASE + AT91RM92_PMC_BASE, AT91RM92_PMC_SIZE, + AT91RM92_IRQ_SYSTEM + }, + { + "at91_aic", 0, + AT91RM92_BASE + AT91RM92_AIC_BASE, AT91RM92_AIC_SIZE, + 0 // Interrupt controller has no interrupts! + }, + { + "at91_rtc", 0, + AT91RM92_BASE + AT91RM92_RTC_BASE, AT91RM92_RTC_SIZE, + AT91RM92_IRQ_SYSTEM + }, + { + "at91_mc", 0, + AT91RM92_BASE + AT91RM92_MC_BASE, AT91RM92_MC_SIZE, + AT91RM92_IRQ_SYSTEM + }, + + // All other devices + { + "at91_tc", 0, + AT91RM92_BASE + AT91RM92_TC0_BASE, AT91RM92_TC_SIZE, + AT91RM92_IRQ_TC0, AT91RM92_IRQ_TC1, AT91RM92_IRQ_TC2 + }, + { + "at91_tc", 1, + AT91RM92_BASE + AT91RM92_TC1_BASE, AT91RM92_TC_SIZE, + AT91RM92_IRQ_TC3, AT91RM92_IRQ_TC4, AT91RM92_IRQ_TC5 + }, + { + "at91_udp", 0, + AT91RM92_BASE + AT91RM92_UDP_BASE, AT91RM92_UDP_SIZE, + AT91RM92_IRQ_UDP + }, + { + "at91_mci", 0, + AT91RM92_BASE + AT91RM92_MCI_BASE, AT91RM92_MCI_SIZE, + AT91RM92_IRQ_MCI + }, + { + "at91_twi", 0, + AT91RM92_BASE + AT91RM92_TWI_BASE, AT91RM92_TWI_SIZE, + AT91RM92_IRQ_TWI + }, + { + "ate", 0, + AT91RM92_BASE + AT91RM92_EMAC_BASE, AT91RM92_EMAC_SIZE, + AT91RM92_IRQ_EMAC + }, + { + "uart", 0, + AT91RM92_BASE + AT91RM92_DBGU_BASE, AT91RM92_DBGU_SIZE, + AT91RM92_IRQ_SYSTEM + }, + { + "uart", 1, + AT91RM92_BASE + AT91RM92_USART0_BASE, AT91RM92_USART_SIZE, + AT91RM92_IRQ_USART0 + }, + { + "uart", 2, + AT91RM92_BASE + AT91RM92_USART1_BASE, AT91RM92_USART_SIZE, + AT91RM92_IRQ_USART1 + }, + { + "uart", 3, + AT91RM92_BASE + AT91RM92_USART2_BASE, AT91RM92_USART_SIZE, + AT91RM92_IRQ_USART2 + }, + { + "uart", 4, + AT91RM92_BASE + AT91RM92_USART3_BASE, AT91RM92_USART_SIZE, + AT91RM92_IRQ_USART3 + }, + { + "at91_ssc", 0, + AT91RM92_BASE + AT91RM92_SSC0_BASE, AT91RM92_SSC_SIZE, + AT91RM92_IRQ_SSC0 + }, + { + "at91_ssc", 1, + AT91RM92_BASE + AT91RM92_SSC1_BASE, AT91RM92_SSC_SIZE, + AT91RM92_IRQ_SSC1 + }, + { + "at91_ssc", 2, + AT91RM92_BASE + AT91RM92_SSC2_BASE, AT91RM92_SSC_SIZE, + AT91RM92_IRQ_SSC2 + }, + { + "at91_spi", 0, + AT91RM92_BASE + AT91RM92_SPI_BASE, AT91RM92_SPI_SIZE, + AT91RM92_IRQ_SPI + }, + { + "ohci", 0, + AT91RM92_OHCI_BASE, AT91RM92_OHCI_SIZE, + AT91RM92_IRQ_UHP + }, + { 0, 0, 0, 0, 0 } +}; + +static void +at91_cpu_add_builtin_children(device_t dev, struct at91_softc *sc) +{ + int i; + struct cpu_devs *walker; + + // XXX should look at the device id in the DBGU register and + // XXX based on the CPU load in these devices + for (i = 0, walker = at91rm9200_devs; walker->name; i++, walker++) { + at91_add_child(dev, i, walker->name, walker->unit, + walker->mem_base, walker->mem_len, walker->irq0, + walker->irq1, walker->irq2); + } +} + #define NORMDEV 50 static int @@ -276,48 +439,9 @@ bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0x20c, 0xffffffff); /* Disable all interrupts for the SDRAM controller */ bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff); - /* XXX call a function here */ - i = 0; - at91_add_child(dev, i++, "at91_st", 0, 0, 0, AT91RM92_IRQ_SYSTEM); - at91_add_child(dev, i++, "at91_pio", 0, AT91RM92_BASE + // PIOA - AT91RM92_PIOA_BASE, AT91RM92_PMC_SIZE, 1); - at91_add_child(dev, i++, "at91_pio", 1, AT91RM92_BASE + // PIOB - AT91RM92_PIOB_BASE, AT91RM92_PMC_SIZE, 1); - at91_add_child(dev, i++, "at91_pio", 2, AT91RM92_BASE + // PIOC - AT91RM92_PIOC_BASE, AT91RM92_PMC_SIZE, 1); - at91_add_child(dev, i++, "at91_pio", 3, AT91RM92_BASE + // PIOD - AT91RM92_PIOD_BASE, AT91RM92_PMC_SIZE, 1); - at91_add_child(dev, i++, "at91_pmc", 0, AT91RM92_BASE + // PMC - AT91RM92_PMC_BASE, AT91RM92_PMC_SIZE, 1); - at91_add_child(dev, NORMDEV, "at91_udp", 0, AT91RM92_BASE + // UDP - AT91RM92_UDP_BASE, AT91RM92_UDP_SIZE, AT91RM92_IRQ_UDP); - at91_add_child(dev, NORMDEV, "at91_mci", 0, AT91RM92_BASE + // MCI - AT91RM92_MCI_BASE, AT91RM92_MCI_SIZE, AT91RM92_IRQ_MCI); - at91_add_child(dev, NORMDEV, "at91_twi", 0, AT91RM92_BASE + // TWI - AT91RM92_TWI_BASE, AT91RM92_TWI_SIZE, AT91RM92_IRQ_TWI); - at91_add_child(dev, NORMDEV, "ate", 0, AT91RM92_BASE + // EMAC - AT91RM92_EMAC_BASE, AT91RM92_EMAC_SIZE, AT91RM92_IRQ_EMAC); - at91_add_child(dev, NORMDEV, "uart", 0, AT91RM92_BASE + // DBGU - AT91RM92_SYS_BASE + DBGU, DBGU_SIZE, AT91RM92_IRQ_SYSTEM); - at91_add_child(dev, NORMDEV, "uart", 1, AT91RM92_BASE + // USART0 - AT91RM92_USART0_BASE, AT91RM92_USART_SIZE, AT91RM92_IRQ_USART0); - at91_add_child(dev, NORMDEV, "uart", 2, AT91RM92_BASE + // USART1 - AT91RM92_USART1_BASE, AT91RM92_USART_SIZE, AT91RM92_IRQ_USART1); - at91_add_child(dev, NORMDEV, "uart", 3, AT91RM92_BASE + // USART2 - AT91RM92_USART2_BASE, AT91RM92_USART_SIZE, AT91RM92_IRQ_USART2); - at91_add_child(dev, NORMDEV, "uart", 4, AT91RM92_BASE + // USART3 - AT91RM92_USART3_BASE, AT91RM92_USART_SIZE, AT91RM92_IRQ_USART3); - at91_add_child(dev, NORMDEV, "at91_ssc", 0, AT91RM92_BASE + // SSC0 - AT91RM92_SSC0_BASE, AT91RM92_SSC_SIZE, AT91RM92_IRQ_SSC0); - at91_add_child(dev, NORMDEV, "at91_ssc", 1, AT91RM92_BASE + // SSC1 - AT91RM92_SSC1_BASE, AT91RM92_SSC_SIZE, AT91RM92_IRQ_SSC1); - at91_add_child(dev, NORMDEV, "at91_ssc", 2, AT91RM92_BASE + // SSC2 - AT91RM92_SSC2_BASE, AT91RM92_SSC_SIZE, AT91RM92_IRQ_SSC2); - at91_add_child(dev, NORMDEV, "at91_spi", 0, AT91RM92_BASE + // SPI - AT91RM92_SPI_BASE, AT91RM92_SPI_SIZE, AT91RM92_IRQ_SPI); - // Not sure that the following belongs on this bus. - at91_add_child(dev, NORMDEV, "ohci", 0, // UHP - AT91RM92_OHCI_BASE, AT91RM92_OHCI_SIZE, AT91RM92_IRQ_UHP); + + at91_cpu_add_builtin_children(dev, sc); + bus_generic_probe(dev); bus_generic_attach(dev); enable_interrupts(I32_bit | F32_bit); ==== //depot/projects/arm/src/sys/arm/at91/at91rm92reg.h#16 (text+ko) ==== @@ -207,13 +207,10 @@ * PIO */ #define AT91RM92_PIOA_BASE 0xffff400 -#define AT91RM92_PIOA_SIZE 0x200 +#define AT91RM92_PIO_SIZE 0x200 #define AT91RM92_PIOB_BASE 0xffff600 -#define AT91RM92_PIOB_SIZE 0x200 #define AT91RM92_PIOC_BASE 0xffff800 -#define AT91RM92_PIOC_SIZE 0x200 #define AT91RM92_PIOD_BASE 0xffffa00 -#define AT91RM92_PIOD_SIZE 0x200 /* * PMC @@ -285,6 +282,18 @@ /* Timer */ +#define AT91RM92_AIC_BASE 0xffff000 +#define AT91RM92_AIC_SIZE 0x200 + +#define AT91RM92_DBGU_BASE 0xffff200 +#define AT91RM92_DBGU_SIZE 0x200 + +#define AT91RM92_RTC_BASE 0xffffe00 +#define AT91RM92_RTC_SIZE 0x100 + +#define AT91RM92_MC_BASE 0xfffff00 +#define AT91RM92_MC_SIZE 0x100 + #define AT91RM92_ST_BASE 0xffffd00 #define AT91RM92_ST_SIZE 0x100 @@ -317,13 +326,12 @@ #define AT91RM92_UDP_SIZE 0x4000 #define AT91RM92_TC0_BASE 0xffa0000 -#define AT91RM92_TC0_SIZE 0x4000 +#define AT91RM92_TC_SIZE 0x4000 #define AT91RM92_TC0C0_BASE 0xffa0000 #define AT91RM92_TC0C1_BASE 0xffa0040 #define AT91RM92_TC0C2_BASE 0xffa0080 #define AT91RM92_TC1_BASE 0xffa4000 -#define AT91RM92_TC1_SIZE 0x4000 #define AT91RM92_TC1C0_BASE 0xffa4000 #define AT91RM92_TC1C1_BASE 0xffa4040 #define AT91RM92_TC1C2_BASE 0xffa4080
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