Date: Tue, 21 Mar 1995 22:30:44 -0800 (PST) From: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> To: bde@zeta.org.au (Bruce Evans) Cc: davidg@freefall.cdrom.com, CVS-commiters@freefall.cdrom.com, cvs-sys@freefall.cdrom.com Subject: Re: cvs commit: src/sys/i386/isa wd.c wdreg.h Message-ID: <199503220630.WAA07607@gndrsh.aac.dev.com> In-Reply-To: <199503220610.QAA04588@godzilla.zeta.org.au> from "Bruce Evans" at Mar 22, 95 04:10:18 pm
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> > >> Correct delay to use port 0x84, reading the status register > >> might not be a long enough delay. > > >Port 0x84 will not cause the 1.25uS delay on some PCI motherboards, > >I beleive all Intel Neptune and Triton based boards know that this > >is not an ISA address and end up running only a PCI I/O cycle for > >it. > > What are the cycle timings for all PC buses? > > ISA: 6 min + normally 4 extra = 1.25uS at 8MHz ? 4 min + I/O recovery cycles (minimum is typically 5) @ 6.0 to 16.0Mhz. Very few I/O cards/machines will run above 10 Mhz. > EISA? 4 min at 8.0 Mhz +/- 5% > PCI? Oh joy, this gets complicated. A ``fast back-to-back transaction'' can run in 2 clocks. A more typical PCI bus transfer is 4 clocks for a read a 3 clocks for a write, for ``fast DEVSEL devices'', add one clock each for ``MED, SLOW, and SUB''. All devices must respond with DEVSEL within 3 cycles of FRAME assertion. Note devices have a syncronous ready signal to insert wait states. These can cause transactions to be quite long (80 CLOCKS is what the award bios defaults to as a maximum for these). Now the fun part of the PCI spec. The clock can be anything from DC to 33 Mhz, and can change frequence while the system is running if you want to, so long as the clock edges remain clean. I have seen some motherboards that allow you to run the PCI bus at 16.5MHZ. Guess this is for some stupid slow PCI card that might now work at 33 Mhz. You are not going to be able to get any predictable timing out of PCI bus devices. :-(. -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Custom computers for FreeBSD
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