Date: Thu, 2 Jan 2025 09:10:49 GMT From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-main@FreeBSD.org Subject: git: 4c6eff7216f2 - main - cad/verilator: update 5.030 =?utf-8?Q?=E2=86=92?= 5.032 Message-ID: <202501020910.5029AnIN024506@gitrepo.freebsd.org>
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The branch main has been updated by yuri: URL: https://cgit.FreeBSD.org/ports/commit/?id=4c6eff7216f2333d68d81ddd4d22f97b5e68a5b4 commit 4c6eff7216f2333d68d81ddd4d22f97b5e68a5b4 Author: Yuri Victorovich <yuri@FreeBSD.org> AuthorDate: 2025-01-02 08:48:53 +0000 Commit: Yuri Victorovich <yuri@FreeBSD.org> CommitDate: 2025-01-02 08:48:53 +0000 cad/verilator: update 5.030 → 5.032 Reported by: portscout --- cad/verilator/Makefile | 2 +- cad/verilator/distinfo | 6 +++--- cad/verilator/pkg-plist | 1 + 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile index dd27f3b3509a..ec9fbd1d7d65 100644 --- a/cad/verilator/Makefile +++ b/cad/verilator/Makefile @@ -1,6 +1,6 @@ PORTNAME= verilator DISTVERSIONPREFIX= v -DISTVERSION= 5.030 +DISTVERSION= 5.032 CATEGORIES= cad MAINTAINER= yuri@FreeBSD.org diff --git a/cad/verilator/distinfo b/cad/verilator/distinfo index a16210d88b90..6c85bf334a08 100644 --- a/cad/verilator/distinfo +++ b/cad/verilator/distinfo @@ -1,3 +1,3 @@ -TIMESTAMP = 1730089848 -SHA256 (verilator-verilator-v5.030_GH0.tar.gz) = b9e7e97257ca3825fcc75acbed792b03c3ec411d6808ad209d20917705407eac -SIZE (verilator-verilator-v5.030_GH0.tar.gz) = 32546625 +TIMESTAMP = 1735791920 +SHA256 (verilator-verilator-v5.032_GH0.tar.gz) = 5a262564b10be8bdb31ff4fb67d77bcf5f52fc1b4e6c88d5ca3264fb481f1e41 +SIZE (verilator-verilator-v5.032_GH0.tar.gz) = 32584297 diff --git a/cad/verilator/pkg-plist b/cad/verilator/pkg-plist index 7ff729878157..99cff59b2848 100644 --- a/cad/verilator/pkg-plist +++ b/cad/verilator/pkg-plist @@ -95,6 +95,7 @@ share/man/man1/verilator_profcfunc.1.gz %%DATADIR%%/include/verilated_sc.h %%DATADIR%%/include/verilated_sc_trace.h %%DATADIR%%/include/verilated_std.sv +%%DATADIR%%/include/verilated_std_waiver.vlt %%DATADIR%%/include/verilated_sym_props.h %%DATADIR%%/include/verilated_syms.h %%DATADIR%%/include/verilated_threads.cpp
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