Date: Sun, 17 Aug 2014 01:28:03 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r270075 - in stable/10/sys: arm/arm arm/include conf dev/fdt dev/ofw sys Message-ID: <201408170128.s7H1S344081448@svn.freebsd.org>
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Author: ian Date: Sun Aug 17 01:28:03 2014 New Revision: 270075 URL: http://svnweb.freebsd.org/changeset/base/270075 Log: MFC r269594, r269596, r269597, r269598, r269605, r269606: Set ofwbus and simplebus to attach during BUS_PASS_BUS. Define names that drivers can use to adjust their position relative to other drivers within a BUS_PASS Adjust ofwbus and simplebus to attach at BUS_PASS_ORDER_MIDDLE, so that a platform can attach some other bus first if necessary. Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU. Attach arm generic interrupt and timer drivers in the middle of BUS_PASS_INTERRUPT and BUS_PASS_TIMER, respectively. Add an arm option, ARM_DEVICE_MULTIPASS, used to opt-in to multi-pass device attachment on arm platforms. If this is defined, nexus attaches early in BUS_PASS_BUS, and other busses and devices attach later, in the pass number they are set up for. Without it defined, nexus attaches in BUS_PASS_DEFAULT and thus so does everything else, which is status quo. Modified: stable/10/sys/arm/arm/generic_timer.c stable/10/sys/arm/arm/gic.c stable/10/sys/arm/arm/mpcore_timer.c stable/10/sys/arm/arm/nexus.c stable/10/sys/arm/arm/pl190.c stable/10/sys/arm/arm/pl310.c stable/10/sys/arm/include/pl310.h stable/10/sys/conf/options.arm stable/10/sys/dev/fdt/simplebus.c stable/10/sys/dev/ofw/ofwbus.c stable/10/sys/sys/bus.h Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/arm/generic_timer.c ============================================================================== --- stable/10/sys/arm/arm/generic_timer.c Sun Aug 17 01:23:52 2014 (r270074) +++ stable/10/sys/arm/arm/generic_timer.c Sun Aug 17 01:28:03 2014 (r270075) @@ -343,7 +343,8 @@ static driver_t arm_tmr_driver = { static devclass_t arm_tmr_devclass; -DRIVER_MODULE(timer, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0); +EARLY_DRIVER_MODULE(timer, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0, + BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); void DELAY(int usec) Modified: stable/10/sys/arm/arm/gic.c ============================================================================== --- stable/10/sys/arm/arm/gic.c Sun Aug 17 01:23:52 2014 (r270074) +++ stable/10/sys/arm/arm/gic.c Sun Aug 17 01:28:03 2014 (r270075) @@ -263,7 +263,8 @@ static driver_t arm_gic_driver = { static devclass_t arm_gic_devclass; -DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0); +EARLY_DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0, + BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); static void gic_post_filter(void *arg) Modified: stable/10/sys/arm/arm/mpcore_timer.c ============================================================================== --- stable/10/sys/arm/arm/mpcore_timer.c Sun Aug 17 01:23:52 2014 (r270074) +++ stable/10/sys/arm/arm/mpcore_timer.c Sun Aug 17 01:28:03 2014 (r270075) @@ -382,7 +382,8 @@ static driver_t arm_tmr_driver = { static devclass_t arm_tmr_devclass; -DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0); +EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0, + BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); /* * Handle a change in clock frequency. The mpcore timer runs at half the CPU Modified: stable/10/sys/arm/arm/nexus.c ============================================================================== --- stable/10/sys/arm/arm/nexus.c Sun Aug 17 01:23:52 2014 (r270074) +++ stable/10/sys/arm/arm/nexus.c Sun Aug 17 01:28:03 2014 (r270075) @@ -125,7 +125,12 @@ static driver_t nexus_driver = { nexus_methods, 1 /* no softc */ }; +#ifdef ARM_DEVICE_MULTIPASS +EARLY_DRIVER_MODULE(nexus, root, nexus_driver, nexus_devclass, 0, 0, + BUS_PASS_BUS + BUS_PASS_ORDER_EARLY); +#else DRIVER_MODULE(nexus, root, nexus_driver, nexus_devclass, 0, 0); +#endif static int nexus_probe(device_t dev) Modified: stable/10/sys/arm/arm/pl190.c ============================================================================== --- stable/10/sys/arm/arm/pl190.c Sun Aug 17 01:23:52 2014 (r270074) +++ stable/10/sys/arm/arm/pl190.c Sun Aug 17 01:28:03 2014 (r270075) @@ -152,7 +152,8 @@ static driver_t pl190_intc_driver = { static devclass_t pl190_intc_devclass; -DRIVER_MODULE(intc, simplebus, pl190_intc_driver, pl190_intc_devclass, 0, 0); +EARLY_DRIVER_MODULE(intc, simplebus, pl190_intc_driver, pl190_intc_devclass, + 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); int arm_get_next_irq(int last_irq) Modified: stable/10/sys/arm/arm/pl310.c ============================================================================== --- stable/10/sys/arm/arm/pl310.c Sun Aug 17 01:23:52 2014 (r270074) +++ stable/10/sys/arm/arm/pl310.c Sun Aug 17 01:28:03 2014 (r270075) @@ -378,6 +378,44 @@ pl310_set_way_sizes(struct pl310_softc * g_l2cache_size = g_way_size * g_ways_assoc; } +/* + * Setup interrupt handling. This is done only if the cache controller is + * disabled, for debugging. We set counters so when a cache event happens we'll + * get interrupted and be warned that something is wrong, because no cache + * events should happen if we're disabled. + */ +static void +pl310_config_intr(void *arg) +{ + struct pl310_softc * sc; + + sc = arg; + + /* activate the interrupt */ + bus_setup_intr(sc->sc_dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, + pl310_filter, NULL, sc, &sc->sc_irq_h); + + /* Cache Line Eviction for Counter 0 */ + pl310_write4(sc, PL310_EVENT_COUNTER0_CONF, + EVENT_COUNTER_CONF_INCR | EVENT_COUNTER_CONF_CO); + /* Data Read Request for Counter 1 */ + pl310_write4(sc, PL310_EVENT_COUNTER1_CONF, + EVENT_COUNTER_CONF_INCR | EVENT_COUNTER_CONF_DRREQ); + + /* Enable and clear pending interrupts */ + pl310_write4(sc, PL310_INTR_CLEAR, INTR_MASK_ECNTR); + pl310_write4(sc, PL310_INTR_MASK, INTR_MASK_ALL); + + /* Enable counters and reset C0 and C1 */ + pl310_write4(sc, PL310_EVENT_COUNTER_CTRL, + EVENT_COUNTER_CTRL_ENABLED | + EVENT_COUNTER_CTRL_C0_RESET | + EVENT_COUNTER_CTRL_C1_RESET); + + config_intrhook_disestablish(sc->sc_ich); + free(sc->sc_ich, M_DEVBUF); +} + static int pl310_probe(device_t dev) { @@ -416,10 +454,6 @@ pl310_attach(device_t dev) pl310_softc = sc; mtx_init(&sc->sc_mtx, "pl310lock", NULL, MTX_SPIN); - /* activate the interrupt */ - bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, - pl310_filter, NULL, sc, &sc->sc_irq_h); - cache_id = pl310_read4(sc, PL310_CACHE_ID); sc->sc_rtl_revision = (cache_id >> CACHE_ID_RELEASE_SHIFT) & CACHE_ID_RELEASE_MASK; @@ -466,28 +500,14 @@ pl310_attach(device_t dev) if (bootverbose) pl310_print_config(sc); } else { - /* - * Set counters so when cache event happens we'll get interrupt - * and be warned that something is off. - */ - - /* Cache Line Eviction for Counter 0 */ - pl310_write4(sc, PL310_EVENT_COUNTER0_CONF, - EVENT_COUNTER_CONF_INCR | EVENT_COUNTER_CONF_CO); - /* Data Read Request for Counter 1 */ - pl310_write4(sc, PL310_EVENT_COUNTER1_CONF, - EVENT_COUNTER_CONF_INCR | EVENT_COUNTER_CONF_DRREQ); - - /* Enable and clear pending interrupts */ - pl310_write4(sc, PL310_INTR_CLEAR, INTR_MASK_ECNTR); - pl310_write4(sc, PL310_INTR_MASK, INTR_MASK_ALL); - - /* Enable counters and reset C0 and C1 */ - pl310_write4(sc, PL310_EVENT_COUNTER_CTRL, - EVENT_COUNTER_CTRL_ENABLED | - EVENT_COUNTER_CTRL_C0_RESET | - EVENT_COUNTER_CTRL_C1_RESET); - + malloc(sizeof(*sc->sc_ich), M_DEVBUF, M_WAITOK); + sc->sc_ich->ich_func = pl310_config_intr; + sc->sc_ich->ich_arg = sc; + if (config_intrhook_establish(sc->sc_ich) != 0) { + device_printf(dev, + "config_intrhook_establish failed\n"); + return(ENXIO); + } device_printf(dev, "L2 Cache disabled\n"); } @@ -514,4 +534,6 @@ static driver_t pl310_driver = { }; static devclass_t pl310_devclass; -DRIVER_MODULE(pl310, simplebus, pl310_driver, pl310_devclass, 0, 0); +EARLY_DRIVER_MODULE(pl310, simplebus, pl310_driver, pl310_devclass, 0, 0, + BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE); + Modified: stable/10/sys/arm/include/pl310.h ============================================================================== --- stable/10/sys/arm/include/pl310.h Sun Aug 17 01:23:52 2014 (r270074) +++ stable/10/sys/arm/include/pl310.h Sun Aug 17 01:28:03 2014 (r270075) @@ -137,6 +137,8 @@ #define POWER_CTRL_ENABLE_GATING (1 << 0) #define POWER_CTRL_ENABLE_STANDBY (1 << 1) +struct intr_config_hook; + struct pl310_softc { device_t sc_dev; struct resource *sc_mem_res; @@ -145,6 +147,7 @@ struct pl310_softc { int sc_enabled; struct mtx sc_mtx; u_int sc_rtl_revision; + struct intr_config_hook *sc_ich; }; /** Modified: stable/10/sys/conf/options.arm ============================================================================== --- stable/10/sys/conf/options.arm Sun Aug 17 01:23:52 2014 (r270074) +++ stable/10/sys/conf/options.arm Sun Aug 17 01:28:03 2014 (r270075) @@ -1,6 +1,7 @@ #$FreeBSD$ ARM9_CACHE_WRITE_THROUGH opt_global.h ARM_CACHE_LOCK_ENABLE opt_global.h +ARM_DEVICE_MULTIPASS opt_global.h ARM_KERN_DIRECTMAP opt_vm.h ARM_L2_PIPT opt_global.h ARM_MANY_BOARD opt_global.h Modified: stable/10/sys/dev/fdt/simplebus.c ============================================================================== --- stable/10/sys/dev/fdt/simplebus.c Sun Aug 17 01:23:52 2014 (r270074) +++ stable/10/sys/dev/fdt/simplebus.c Sun Aug 17 01:28:03 2014 (r270075) @@ -121,8 +121,10 @@ static driver_t simplebus_driver = { sizeof(struct simplebus_softc) }; static devclass_t simplebus_devclass; -DRIVER_MODULE(simplebus, ofwbus, simplebus_driver, simplebus_devclass, 0, 0); -DRIVER_MODULE(simplebus, simplebus, simplebus_driver, simplebus_devclass, 0, 0); +EARLY_DRIVER_MODULE(simplebus, ofwbus, simplebus_driver, simplebus_devclass, + 0, 0, BUS_PASS_BUS); +EARLY_DRIVER_MODULE(simplebus, simplebus, simplebus_driver, simplebus_devclass, + 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); static int simplebus_probe(device_t dev) Modified: stable/10/sys/dev/ofw/ofwbus.c ============================================================================== --- stable/10/sys/dev/ofw/ofwbus.c Sun Aug 17 01:23:52 2014 (r270074) +++ stable/10/sys/dev/ofw/ofwbus.c Sun Aug 17 01:28:03 2014 (r270075) @@ -136,7 +136,8 @@ static driver_t ofwbus_driver = { sizeof(struct ofwbus_softc) }; static devclass_t ofwbus_devclass; -DRIVER_MODULE(ofwbus, nexus, ofwbus_driver, ofwbus_devclass, 0, 0); +EARLY_DRIVER_MODULE(ofwbus, nexus, ofwbus_driver, ofwbus_devclass, 0, 0, + BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); MODULE_VERSION(ofwbus, 1); static const char *const ofwbus_excl_name[] = { Modified: stable/10/sys/sys/bus.h ============================================================================== --- stable/10/sys/sys/bus.h Sun Aug 17 01:23:52 2014 (r270074) +++ stable/10/sys/sys/bus.h Sun Aug 17 01:28:03 2014 (r270075) @@ -569,6 +569,12 @@ void bus_data_generation_update(void); #define BUS_PASS_SCHEDULER 60 /* Start scheduler. */ #define BUS_PASS_DEFAULT __INT_MAX /* Everything else. */ +#define BUS_PASS_ORDER_FIRST 0 +#define BUS_PASS_ORDER_EARLY 2 +#define BUS_PASS_ORDER_MIDDLE 5 +#define BUS_PASS_ORDER_LATE 7 +#define BUS_PASS_ORDER_LAST 9 + extern int bus_current_pass; void bus_set_pass(int pass);
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