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Date:      Mon, 18 May 1998 08:18:41 +1000 (EST)
From:      Peter Jeremy <peter.jeremy@alcatel.com.au>
To:        freebsd-hackers@FreeBSD.ORG
Subject:   Pentium F00F bug
Message-ID:  <199805172218.IAA03007@gsms01.alcatel.com.au>

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There's an interesting article on the F00F bug by Robert Collins
<rcollins@x86.org> in May Dr Dobbs Journal.  He discusses the adverse
impacts of Intel's recommended work-arounds (one of which we use).

Robert suggests alternative solutions, which rely on interactions
between the bug and the cache, rather than the page fault microcode.
These solutions uses the same cross-page IDT alignment as Intel, but
mark the first page non-cacheable - either set PTE.PCD=1 or PTE.PWT=1.

The major benefit of this approach is that the exception handlers all
vector directly to the appropriate interrupt handler - no kludges in
the page-fault handler are needed.

Has anyone looked into using these work-arounds instead?

Peter
--
Peter Jeremy (VK2PJ)                    peter.jeremy@alcatel.com.au
Alcatel Australia Limited
41 Mandible St                          Phone: +61 2 9690 5019
ALEXANDRIA  NSW  2015                   Fax:   +61 2 9690 5247

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